Configuration Handbook - Kamami.pl

Configuring Stratix III DevicesTable 11–8 shows the fast AS timing parameters for Stratix III devices.Table 11–8. Fast AS Timing Parameters for Stratix III DevicesSymbol Parameter Minimum Typical Maximum Unitst CF2ST1 nCONFIG high to nSTATUS high — — 100 μst DSUData setup time before falling edgeon DCLK7 — — nst DHData hold time after falling edge onDCLK0 — — nst CH DCLK high time 10 — — nst CL DCLK low time 10 — — nst CD2UM CONF_DONE high to user mode 20 — 100 μsPassive SerialConfigurationYou can program PS configuration of Stratix III devices using anintelligent host, such as a MAX II device or microprocessor with flashmemory, an Altera configuration device, or a download cable. In the PSscheme, an external host (a MAX II device, embedded processor,configuration device, or host PC) controls configuration. As the largestenhanced configuration device supports 16 MBits of configurationbitstream, you may need to use the MAX II device, or use amicroprocessor using the flash memory configuration method, or utilizethe compression feature, to reduce the configuration file size of largeStratix III devices. Configuration data is clocked into the target Stratix IIIdevice via the DATA0 pin at each rising edge of DCLK.1 The Stratix III decompression and design security features arefully available when configuring your Stratix III device using PSmode.Table 11–9 shows the MSEL pin settings when using the PS configurationscheme.Table 11–9. Stratix III MSEL Pin Settings for PS ConfigurationSchemesConfiguration Scheme MSEL2 MSEL1 MSEL0PS 0 1 0Altera Corporation 11–41May 2007 Stratix III Device Handbook, Volume 1