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Configuration Handbook - Kamami.pl

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Fast Passive Parallel <strong>Configuration</strong>device also goes through a POR delay to allow the power sup<strong>pl</strong>y tostabilize. You can set the POR time for enhanced configuration devices toeither 100 ms or 2 ms, depending on its PORSEL pin setting. If the PORSELpin is connected to GND, the POR delay is 100 ms. If the PORSEL pin isconnected to V CC , the POR delay is 2 ms. During this time, theconfiguration device drives its OE pin low. This low signal delaysconfiguration because the OE pin is connected to the target device'snSTATUS pin.1 When selecting a POR time, you need to ensure that the devicecom<strong>pl</strong>etes power-up before the enhanced configuration deviceexits POR. Altera recommends that you use a 12 ms POR timefor the Stratix III device, and that you use a 100 ms POR time forthe enhanced configuration device.When both devices com<strong>pl</strong>ete POR, they release their open-drain OE ornSTATUS pin, which is then pulled high by a pull-up resistor. Once thedevice successfully exits POR, all user I/O pins continue to be tri-stated.If nIO_pullup is driven low during power-up and configuration, theuser I/O pins and dual-purpose I/O pins will have weak pull-upresistors, which are on (after POR) before and during configuration. IfnIO_pullup is driven high, the weak pull-up resistors are disabled.When the power sup<strong>pl</strong>ies have reached the appropriate operatingvoltages, the target device senses the low-to-high transition on nCONFIGand initiates the configuration cycle. The configuration cycle consists ofthree stages: reset, configuration, and initialization. While nCONFIG ornSTATUS are low, the device is in reset. You can delay the beginning ofconfiguration by holding the nCONFIG or nSTATUS pin low.1 V CC , V CCIO , V CCPGM , and V CCPD of the banks where theconfiguration and JTAG pins reside need to be fully powered tothe appropriate voltage levels in order to begin theconfiguration process.When nCONFIG goes high, the device comes out of reset and releases thenSTATUS pin, which is pulled high by a pull-up resistor. Enhancedconfiguration devices have an optional internal pull-up resistor on the OEpin. This option is available in the Quartus II software from the Generaltab of the Device and Pin Options dialog box. If you do not use thisinternal pull-up resistor, an external 10-kΩ pull-up resistor on theOE-nSTATUS line is required. Once nSTATUS is released, the device isready to receive configuration data and the configuration stage begins.11–24 Altera CorporationStratix III Device <strong>Handbook</strong>, Volume 1 May 2007

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