Configuration Handbook - Kamami.pl

Timing InformationTable 2–12. Enhanced Configuration Device Configuration ParametersSymbol Parameter Condition Min Typ Max Unitf DCLK DCLK frequency 40% duty cycle 66.7 MHzt DCLK DCLK period 15 nst HC DCLK duty cycle high time 40% duty cycle 6 nst LC DCLK duty cycle low time 40% duty cycle 6 nst CE OE to first DCLK delay 40 nst OE OE to first DATA available 40 nst OH DCLK rising edge to DATA change (1) nst CF (2) OE assert to DCLK disable delay 277 nst DF (2) OE assert to DATA disable delay 277 nst RE (3) DCLK rising edge to OE 60 nst LOE OE assert time to assure reset 60 nsf ECLK EXCLK input frequency 40% duty cycle 100 MHzt ECLK EXCLK input period 10 nst ECLKH EXCLK input duty cycle high time 40% duty cycle 4 nst ECLKL EXCLK input duty cycle low time 40% duty cycle 4 nst ECLKR EXCLK input rise time 100 MHz 3 nst ECLKF EXCLK input fall time 100 MHz 3 nst POR (4) POR time 2 ms 1 2 3 ms100 ms 70 100 120 msNotes to Table 2–12:(1) To calculate t OH , use the following equation: t OH = 0.5 (DCLK period) - 2.5 ns.(2) This parameter is used for CRC error detection by the FPGA.(3) This parameter is used for CONF_DONE error detection by the enhanced configuration device.(4) The FPGA V CCINT ramp time should be less than 1-ms for 2-ms POR, and it should be less than 70 ms for 100-msPOR.2–32 Altera CorporationConfiguration Handbook, Volume 2 May 2007