Configuration Handbook - Kamami.pl

Functional Description■■■■■■■■Hardware compliant with IEEE Std. 1532 in-systemprogrammability (ISP) specificationSupports ISP via Jam Standard Test and Programming Language(STAPL)Supports Joint Test Action Group (JTAG) boundary scannINIT_CONF pin allows private JTAG instruction to initiate FPGAconfigurationInternal pull-up resistor on nINIT_CONF always enabledUser programmable weak internal pull-up resistors on nCS and OEpinsInternal weak pull-up resistors on external flash interface addressand control lines, bus hold on data linesStandby mode with reduced power consumptionfFor more information on FPGA configuration schemes and advancedfeatures, refer to the appropriate FPGA family chapter in theConfiguration Handbook.FunctionalDescriptionfThe Altera enhanced configuration device is a single-device, high-speed,advanced configuration solution for very high-density FPGAs. The coreof an enhanced configuration device is divided into two major blocks, aconfiguration controller and a flash memory. The flash memory is used tostore configuration data for systems made up of one or more AlteraFPGAs. Unused portions of the flash memory can be used to storeprocessor code or data that can be accessed via the external flash interfaceafter FPGA configuration is complete.Altera has introduced additional enhanced configuration devices. Fordetails, please refer to the Process Change Notification PCN0506:Addition of Intel Flash Memory As Source For EPC4, EPC8 & EPC16Enhanced Configuration Devices and Using Intel Flash Memory Based EPC4,EPC8 and EPC16 white paper.EPC devices support three different types of flash memory. Table 2–1shows the supported flash memory for all EPC devices.Table 2–1. Enhanced Configuration Devices Flash Memory (Part 1 of 2)DeviceEPC16EPC8Flash MemoryIntel Flash (1)Sharp FlashIntel Flash (1)Sharp Flash2–2 Altera CorporationConfiguration Handbook, Volume 2 May 2007