Configuration Handbook - Kamami.pl

Passive Parallel Synchronous ConfigurationThe configuration cycle consists of 3 stages: reset, configuration, andinitialization. While nCONFIG or nSTATUS are low, the device is in reset.To initiate configuration in this scheme, the microprocessor mustgenerate a low-to-high transition on the nCONFIG pin.1 VCCINT and VCCIO pins on the banks where the configurationand JTAG pins reside need to be fully powered to theappropriate voltage levels in order to begin the configurationprocess.When nCONFIG goes high, the device comes out of reset and releases theopen-drain nSTATUS pin, which is then pulled high by an external 1-kΩpull-up resistor. Once nSTATUS is released the FPGA is ready to receiveconfiguration data and the configuration stage begins. When nSTATUS ispulled high, the microprocessor should place the configuration data onebyte at a time on the DATA[7..0] pins. New configuration data shouldbe sent to the FPGA every eight DCLK cycles.The Mercury, APEX 20K (2.5 V), ACEX 1K or FLEX 10K device receivesconfiguration data on its DATA[7..0] pins and the clock is received onthe DCLK pin. On the first rising DCLK edge, a byte of configuration datais latched into the target device; the subsequent eight falling DCLK edgesserialize the configuration data in the device. On the ninth rising clockedge, the next byte of configuration data is latched and serialized into thetarget device.Data is clocked into the target device until CONF_DONE goes high. Afterthe FPGA has received all configuration data successfully, it releases theopen-drain CONF_DONE pin, which is pulled high by an external 1-kΩpull-up resistor. A low-to-high transition on CONF_DONE indicatesconfiguration is complete and initialization of the device can begin.In Mercury and APEX 20K devices, the initialization process issynchronous and can be clocked by its internal oscillator (typically10 MHz) or by the optional CLKUSR pin. By default, the internal oscillatoris the clock source for initialization. If the internal oscillator is used, theMercury or APEX 20K device will take care to provide itself with enoughclock cycles for proper initialization. Therefore, if the internal oscillator isthe initialization clock source, sending the entire configuration file to thedevice is sufficient to configure and initialize the device. Driving DCLK tothe device after configuration is complete does not affect deviceoperation.8–36 Altera CorporationConfiguration Handbook, Volume 1 August 2005