Configuration Handbook - Kamami.pl

Introduction1 For more information on EPC2 configuration devices, refer tothe Configuration Devices for SRAM-Based LUT Devices Data Sheetchapter in volume 2 of the Configuration Handbook.The configuration scheme is selected by driving the Stratix II orStratix II GX device MSEL pins either high or low as shown in Table 7–1.The MSEL pins are powered by the V CCIO power supply of the bank theyreside in. The MSEL[3..0] pins have 9-kΩ internal pull-down resistorsthat are always active. During power-on reset (POR) and duringreconfiguration, the MSEL pins have to be at LVTTL V IL and V IH levels tobe considered a logic low and logic high.1 To avoid any problems with detecting an incorrect configurationscheme, hard-wire the MSEL[] pins to V CCPD and GND, withoutany pull-up or pull-down resistors. Do not drive the MSEL[]pins by a microprocessor or another device.Table 7–1. Stratix II & Stratix II GX Configuration Schemes (Part 1 of 2)Configuration Scheme MSEL3 MSEL2 MSEL1 MSEL0Fast passive parallel (FPP) 0 0 0 0Passive parallel asynchronous (PPA) 0 0 0 1Passive serial (PS) 0 0 1 0Remote system upgrade FPP (1) 0 1 0 0Remote system upgrade PPA (1) 0 1 0 1Remote system upgrade PS (1) 0 1 1 0Fast AS (40 MHz) (2) 1 0 0 0Remote system upgrade fast AS (40 MHz) (2) 1 0 0 1FPP with decompression and/or design securityfeature enabled (3)1 0 1 1Remote system upgrade FPP with decompressionand/or design security feature enabled (1), (3)1 1 0 0AS (20 MHz) (2) 1 1 0 1Remote system upgrade AS (20 MHz) (2) 1 1 1 0JTAG-based configuration (5) (4) (4) (4) (4)7–2 Altera CorporationStratix II Device Handbook, Volume 2 May 2007