Configuration Handbook - Kamami.pl

Configuring Cyclone FPGAsFigure 13–21. JTAG Configuration of Cyclone FPGAs with a MicroprocessorMemoryADDR DATAMicroprocessor(1)(2)(2)Cyclone FPGAnCONFIGDATA0DCLKTDITCKTMSMSEL1MSEL0TDOnSTATUSCONF_DONE(1)(1)V CCVnCE (3) CC 10 kΩnCEO N.C. 10 kΩNotes to Figure 13–21:(1) Connect the nCONFIG, MSEL1, and MSEL0 pins to support a non-JTAGconfiguration scheme. If your design only uses JTAG configuration, connect thenCONFIG pin to V CC and the MSEL1 and MSEL0 pins to ground.(2) Pull DATA0 and DCLK to either high or low.(3) nCE must be connected to GND or driver low for succesful JTAG configuration.fFor more information about JTAG programming in an embeddedenvironment, refer to AN 122: Using JamSTAPL for ISP &ICR via anEmbedded Processor.Configuring Cyclone FPGAs with JRunnerJRunner is a software driver that allows you to configure Altera FPGAs,including Cyclone FPGAs, through the ByteBlaster II or ByteBlasterMVcables in JTAG mode. The programming input file supported is in .rbfformat. JRunner also requires a Chain Description File (.cdf) generated bythe Quartus II software. JRunner is targeted for embedded JTAGconfiguration. The source code has been developed for the Windows NToperating system (OS). You can customize the code to make it run onother platforms. For more information on the JRunner software driver,see JRunner Software Driver: An Embedded Solution to the JTAGConfiguration and the source files on the Altera web site.Jam STAPLJam STAPL, JEDEC standard JESD-71, is a standard file format for insystemprogrammability (ISP) purposes. Jam STAPL supportsprogramming or configuration of programmable devices and testing ofelectronic systems, using the IEEE 1149.1 JTAG interface. Jam STAPL is afreely licensed open standard.Altera Corporation 13–37January 2007 Cyclone Device Handbook, Volume 1