Configuration Handbook - Kamami.pl

Configuration Schemes1 If V CCIO is tied to 3.3-V, both the I/O pins and the JTAG TDO portdrive at 3.3-V levels.Cyclone FPGAs have dedicated JTAG pins. Not only can you performJTAG testing on Cyclone FPGAs before and after, but also duringconfiguration. While other device families do not support JTAG testingduring configuration, Cyclone FPGAs support the BYPASS, IDCODE, andSAMPLE instructions during configuration without interruptingconfiguration. All other JTAG instructions may only be issued by firstinterrupting configuration and reprogramming I/O pins using theCONFIG_IO instruction.The CONFIG_IO instruction allows I/O buffers to be configured via theJTAG port, and when issued, interrupts configuration. This instructionallows you to perform board-level testing prior to configuring theCyclone FPGA or waiting for a configuration device to completeconfiguration. Once configuration has been interrupted and JTAG testingis complete, the part must be reconfigured via JTAG (PULSE_CONFIGinstruction) or by pulsing nCONFIG low.The chip-wide reset and output enable pins on Cyclone FPGAs do notaffect JTAG boundary-scan or programming operations. Toggling thesepins does not affect JTAG operations (other than the usual boundary-scanoperation).13–34 Altera CorporationCyclone Device Handbook, Volume 1 January 2007