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Configuration Handbook - Kamami.pl

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Configuring Stratix II & Stratix II GX DevicesFigure 7–18. Multi-Device PS <strong>Configuration</strong> Using an External HostADDRMemoryDATA0V CC (1)V CC (1)10 kΩ 10 kΩStratix II or Stratix II GXDevice 1Stratix II or Stratix II GXDevice 2External Host(MAX II Device orMicroprocessor)GNDCONF_DONEnSTATUSnCEnCEOMSEL3MSEL2DATA0nCONFIG MSEL1DCLK MSEL0V CCCONF_DONEnSTATUS nCEOnCEMSEL3MSEL2DATA0nCONFIGMSEL1DCLK MSEL0N.C.V CCGNDGNDNote to Figure 7–18:(1) The pull-up resistor should be connected to a sup<strong>pl</strong>y that provides an acceptable input signal for all devices in thechain. V CC should be high enough to meet the V IH specification of the I/O on the device and the external host.In multi-device PS configuration the first device’s nCE pin is connected toGND while its nCEO pin is connected to nCE of the next device in thechain. The last device's nCE input comes from the previous device, whileits nCEO pin is left floating. After the first device com<strong>pl</strong>etes configurationin a multi-device configuration chain, its nCEO pin drives low to activatethe second device's nCE pin, which prompts the second device to beginconfiguration. The second device in the chain begins configuration withinone clock cycle. Therefore, the transfer of data destinations is transparentto the MAX II device. All other configuration pins (nCONFIG, nSTATUS,DCLK, DATA0, and CONF_DONE) are connected to every device in thechain. <strong>Configuration</strong> signals can require buffering to ensure signalintegrity and prevent clock skew problems. Ensure that the DCLK andDATA lines are buffered for every fourth device. Because all deviceCONF_DONE pins are tied together, all devices initialize and enter usermode at the same time.Since all nSTATUS and CONF_DONE pins are tied together, if any devicedetects an error, configuration stops for the entire chain and the entirechain must be reconfigured. For exam<strong>pl</strong>e, if the first device flags an erroron nSTATUS, it resets the chain by pulling its nSTATUS pin low. Thisbehavior is similar to a single device detecting an error.Altera Corporation 7–51May 2007 Stratix II Device <strong>Handbook</strong>, Volume 2

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