Configuration Handbook - Kamami.pl

Device Configuration PinsTable 11–17 describes the dedicated JTAG pins. JTAG pins must be keptstable before and during configuration to prevent accidental loading ofJTAG instructions. If you plan to use the SignalTap II Embedded LogicAnalyzer, you will need to connect the JTAG pins of your device to aJTAG header on your board.Table 11–17. Dedicated JTAG pinsPin Name User Mode Pin Type DescriptionTDI N/A Input Serial input pin for instructions as well as test andprogramming data. Data is shifted in on the rising edge ofTCK. If the JTAG interface is not required on the board, theJTAG circuitry can be disabled by connecting this pin toV CC . This pin uses Schmitt trigger input buffers.TDO N/A Output Serial data output pin for instructions as well as test andprogramming data. Data is shifted out on the falling edgeof TCK. The pin is tri-stated if data is not being shifted outof the device. If the JTAG interface is not required on theboard, the JTAG circuitry can be disabled by leaving thispin unconnected.TMS N/A Input Input pin that provides the control signal to determine thetransitions of the TAP controller state machine. Transitionswithin the state machine occur on the rising edge of TCK.Therefore, TMS must be set up before the rising edge ofTCK. TMS is evaluated on the rising edge of TCK. If theJTAG interface is not required on the board, the JTAGcircuitry can be disabled by connecting this pin to V CC .This pin uses Schmitt trigger input buffers.TCK N/A Input The clock input to the BST circuitry. Some operationsoccur at the rising edge, while others occur at the fallingedge. If the JTAG interface is not required on the board, theJTAG circuitry can be disabled by connecting this pin toGND. This pin uses Schmitt trigger input buffers.TRST N/A Input Active-low input to asynchronously reset the boundaryscancircuit. The TRST pin is optional according to IEEEStd. 1149.1. If the JTAG interface is not required on theboard, the JTAG circuitry can be disabled by connectingthis pin to GND. This pin uses Schmitt trigger input buffers.11–60 Altera CorporationStratix Device Handbook, Volume 2 July 2005