Configuration Handbook - Kamami.pl

Fast Passive Parallel Configuration(FPP) modes. The last byte is required for serial configuration (AS and PS)modes. After the CONF_DONE pin transitions high, CLKUSR is enabledafter the time specified as t CD2CU . After this time period elapses, Stratix IIIdevices require 4,436 clock cycles to initialize properly and enter usermode. Stratix III devices support a CLKUSR f MAX of 100 MHz.An optional INIT_DONE pin is available, which signals the end ofinitialization and the start of user-mode with a low-to-high transition.This Enable INIT_DONE Output option is available in the Quartus IIsoftware from the General tab of the Device and Pin Options dialog box.If you use the INIT_DONE pin, it is high because of an external 10-kΩpull-up resistor when nCONFIG is low and during the beginning ofconfiguration. Once the option bit to enable INIT_DONE is programmedinto the device (during the first frame of configuration data), theINIT_DONE pin goes low. When initialization is complete, theINIT_DONE pin is released and pulled high. The MAX II device must beable to detect this low-to-high transition, which signals the device hasentered user mode. When initialization is complete, the device enters usermode. In user-mode, the user I/O pins no longer have weak pull-upresistors and function as assigned in your design.To ensure DCLK and DATA[7..0] are not left floating at the end ofconfiguration, the MAX II device must drive them either high or low,whichever is convenient on your board. The DATA[7..0] pins areavailable as user I/O pins after configuration. When you select the FPPscheme as a default in the Quartus II software, these I/O pins aretri-stated in user mode. To change this default option in the Quartus IIsoftware, select the Dual-Purpose Pins tab of the Device and Pin Optionsdialog box.The configuration clock (DCLK) speed must be below the specifiedfrequency to ensure correct configuration. No maximum DCLK periodexists, which means you can pause configuration by halting DCLK for anindefinite amount of time.1 If you are using the Stratix III decompression and/or designsecurity feature and need to stop DCLK, it can only be stoppedthree clock cycles after the last data byte was latched into theStratix III device.By stopping DCLK, the configuration circuit allows enough clock cycles toprocess the last byte of latched configuration data. When the clockrestarts, the MAX II device must provide data on the DATA[7..0] pinsprior to sending the first DCLK rising edge.11–14 Altera CorporationStratix III Device Handbook, Volume 1 May 2007