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Configuration Handbook - Kamami.pl

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Configuring APEX II DevicesFigure 6–26. Multi<strong>pl</strong>e-Device PPA <strong>Configuration</strong> Using a Microprocessor When Both FPGAs Receive theSame DataV CC (2)(2) V CC1 kΩV CC (2)1 kΩAddress Decoder1 kΩADDRMemoryADDR DATA[7..0]V CC (2)1 kΩAPEX II DeviceAPEX II DeviceMicroprocessorDATA[7..0]nCS (1)CS (1)CONF_DONEnSTATUSnWSnRSnCONFIGRDYnBSYnCEDCLKMSEL1MSEL0GNDnCEON.C. (3)V CCGNDDATA[7..0]nCS (1)CS (1)CONF_DONEnSTATUSnCEnWSnRSnCONFIGRDYnBSYDCLKnCEO N.C. (3)MSEL1MSEL0V CCNotes to Figure 6–26:(1) If not used, the CS pin can be connected to V CC directly. If not used, the nCS pin can be connected to GND directly.(2) The pull-up resistor should be connected to a sup<strong>pl</strong>y that provides an acceptable input signal for all devices in thechain.(3) The nCEO pins of both devices are left unconnected when configuring the same configuration data into multi<strong>pl</strong>edevices.You can use a single configuration chain to configure APEX II deviceswith other Altera devices that support PPA configuration, such as Stratix,Mercury, APEX 20K, ACEX 1K, and FLEX 10KE devices. To ensure that alldevices in the chain com<strong>pl</strong>ete configuration at the same time or that anerror flagged by one device initiates reconfiguration in all devices, all ofthe device CONF_DONE and nSTATUS pins must be tied together.fFor more information on configuring multi<strong>pl</strong>e Altera devices in the sameconfiguration chain, refer to Configuring Mixed Altera FPGA Chains in the<strong>Configuration</strong> <strong>Handbook</strong>.Figure 6–27 shows the timing waveform for the PPA configurationscheme using a microprocessor.Altera Corporation 6–53August 2005 <strong>Configuration</strong> <strong>Handbook</strong>, Volume 1

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