Configuration Handbook - Kamami.pl

PackageTable 4–27. Serial Configuration Device Pin Description (Part 2 of 2)PinNamePin Numberin 8-PinSOICPackagePin Numberin 16-PinSOICPackagePin TypeDescriptionDCLK 6 16 Input DCLK is provided by the FPGA. This signal provides the timingof the serial interface. The data presented on ASDI is latchedto the serial configuration device, at the falling edge of DCLK.Data on the DATA pin changes after the falling edge of DCLKand is latched into the FPGA on the falling edge.V CC 3, 7, 8 1,2,9 Power Power pins connect to 3.3 V.GND 4 10 Ground Ground pin.PackageAll serial configuration devices are available in 8-pin or 16-pin plasticSOIC package.fFor more information on Altera device packaging including mechanicaldrawing and specifications for this package, see the Altera Device PackageInformation Data Sheet.Ordering CodeTable 4–28 shows the ordering codes for serial configuration devices.Table 4–28. Serial Configuration Device Ordering CodesDevice Ordering Code (1)EPCS1EPCS4EPCS16EPCS64EPCS1SI8EPCS1SI8NEPCS4SI8EPCS4SI8NEPCS16SI16NEPCS16SI8NEPCS64SI16NNote to Table 4–28:(1) N: Lead free.4–40 Altera CorporationConfiguration Handbook, Volume 2 April 2007