Configuration Handbook - Kamami.pl

Passive Parallel Synchronous ConfigurationFigure 8–19. Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10KE PPS Configuration Timing WaveformnCONFIG(1) nSTATUSDCLKt CFG7.5 Cyclestt CLKCF2CKt CHt CL(3)DATA[7..0]ZZt DSUt DHByte 0 Byte 1 Byte n FFUser Mode(3)(4) RDYnBSYt CH2BUser Mode(3)(2) CONF_DONEINIT_DONEUser I/OHigh zHigh zUser Modet CD2UMNotes to Figure 8–19:(1) Upon power-up, the Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10KE device holds nSTATUS low forapproximately 5 µs after V CC reaches its minimum requirement.(2) Upon power-up, before and during configuration, CONF_DONE is low.(3) DATA0 and DCLK should not be left floating after configuration. It should be driven high or low, whichever is moreconvenient. DATA[7..1] and RDYnBSY are available as user I/O pins after configuration and the state of thesespins depends on the design programmed into the device.(4) The RDYnBSY pin is not required in the PPS mode. Configuration data can be sent every 8 DCLK cycles withoutmonitoring this status pin.Tables 8–12 through 8–14 define the timing parameters for Mercury,APEX 20K, ACEX 1K, and FLEX 10K devices for PPS configuration.Table 8–11. PPS Timing Parameters for Mercury Devices (Part 1 of 2)Symbol Parameter Min Max Unitst CF2CD nCONFIG low to CONF_DONE low 200 nst CF2ST0 nCONFIG low to nSTATUS low 200 nst CFG nCONFIG low pulse width 21 µst STATUS nSTATUS low pulse width 10 40 (1) µst CF2ST1 nCONFIG high to nSTATUS high 1 (1) µst CF2CK nCONFIG high to first rising edge on DCLK 45 µst ST2CK nSTATUS high to first rising edge on DCLK 1 µst DSU Data setup time before rising edge on DCLK 10 nst DH Data hold time after rising edge on DCLK 0 nst CH2B First rising DCLK to first rising RDYnBSY (2) 0.75 (3) µs8–42 Altera CorporationConfiguration Handbook, Volume 1 August 2005