Configuration Handbook - Kamami.pl

Passive Parallel Synchronous ConfigurationIn APEX 20KE and APEX 20KC devices, the initialization process issynchronous and can be clocked by its internal oscillator (typically10 MHz) or by the optional CLKUSR pin. By default, the internal oscillatoris the clock source for initialization. If the internal oscillator is used, theAPEX 20KE or APEX 20KC device will take care to provide itself withenough clock cycles for proper initialization. Therefore, if the internaloscillator is the initialization clock source, sending the entireconfiguration file to the device is sufficient to configure and initialize thedevice. Driving DCLK to the device after configuration is complete doesnot affect device operation.You also have the flexibility to synchronize initialization of multipledevices by using the CLKUSR option. The Enable user-supplied start-up clock(CLKUSR) option can be turned on in the Quartus II software from theGeneral tab of the Device & Pin Options dialog box. Supplying a clockon CLKUSR will not affect the configuration process. After allconfiguration data has been accepted and CONF_DONE goes high,APEX 20KE and APEX 20KC devices require 40 clock cycles to initializeproperly.An optional INIT_DONE pin is available, which signals the end ofinitialization and the start of user-mode with a low-to-high transition.This Enable INIT_DONE output option is available in the Quartus IIsoftware from the General tab of the Device & Pin Options dialog box.If the INIT_DONE pin is used it will be high due to an external 10-kΩ pullupresistor when nCONFIG is low and during the beginning ofconfiguration. Once the option bit to enable INIT_DONE is programmedinto the device (during the first frame of configuration data), theINIT_DONE pin will go low. When initialization is complete, theINIT_DONE pin will be released and pulled high. The microprocessormust be able to detect this low-to-high transition which signals the FPGAhas entered user mode. In user-mode, the user I/O pins will no longerhave weak pull-ups and will function as assigned in your design. Wheninitialization is complete, the FPGA enters user mode.To ensure DCLK and DATA0 are not left floating at the end ofconfiguration, the microprocessor must take care to drive them eitherhigh or low, whichever is convenient on your board. The DATA[7..1]pins are available as user I/O pins after configuration. When the PPSscheme is chosen in the Quartus II software, as a default these I/O pinsare tri-stated in user mode and should be driven by the microprocessor.To change this default option in the Quartus II software, select the Dual-Purpose Pins tab of the Device & Pin Options dialog box.7–36 Altera CorporationConfiguration Handbook, Volume 1 August 2005