Configuration Handbook - Kamami.pl

Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data SheetfFor detailed information on using these schemes to configure yourAltera FPGA, refer to the appropriate FPGA family chapter in theConfiguration Handbook.Configuration SignalsTable 2–2 lists the configuration signal connections between the enhancedconfiguration device and Altera FPGAs.Table 2–2. Configuration SignalsEnhancedConfigurationDevice PinAltera FPGAPinDescriptionDATA[] DATA[] Configuration data transmitted from theconfiguration device to the FPGA, which islatched on the rising edge of DCLK.DCLK DCLK Configuration device generated clock used bythe FPGA to latch configuration data providedon the DATA[] pins.nINIT_CONF nCONFIG Open-drain output from the configuration devicethat is used to initiate FPGA reconfigurationusing the initiate configuration (INIT_CONF)JTAG instruction. This connection is not neededif the INIT_CONF JTAG instruction is notneeded. If nINIT_CONF is not connected tonCONFIG, nCONFIG must be tied to V CC eitherdirectly or through a pull-up resistor.OE nSTATUS Open-drain bidirectional configuration statussignal, which is driven low by either deviceduring POR and to signal an error duringconfiguration. Low pulse on OE resets theenhanced configuration device controller.nCS CONF_DONE Configuration done output signal driven by theFPGA.Altera Corporation 2–7May 2007 Configuration Handbook, Volume 2