Configuration Handbook - Kamami.pl

Configuration SchemesFigure 11–13. Parallel Data Transfer in Serial Configuration with a MicroprocessorV CC (1)Memory10 kΩADDR DATA[7..0]V CC (1)10 kΩStratix DeviceStratix DeviceMSEL2MSEL2MSEL1CONF_DONEMSEL0nSTATUSCONF_DONEnSTATUSMSEL1MSEL0MicroprocessorGNDnCEDATA[7..0]nCEOGNDnCEDATA[7..0]nCEOGNDN.C.nCONFIGnCONFIGDCLKDCLKNote to Figure 11–13:(1) You should connect the pull-up resistors to any V CC that meets the Stratix high-level input voltage (V IH )specification.Figure 11–14. Multiple Device Parallel Configuration with the Same Data Using a MicroprocessorV CC (1)Memory10 kΩADDRDATA[7..0]V CC (1)10 kΩStratix DeviceStratix DeviceMSEL2MSEL2CONF_DONEnSTATUSMSEL1MSEL0CONF_DONEnSTATUSMSEL1MSEL0MicroprocessorGNDnCEDATA[7..0]GNDnCEO N.C. (2) GNDnCEDATA[7..0]GNDnCEO N.C. (2)nCONFIGnCONFIGDCLKDCLKNotes to Figure 11–14:(1) You should connect the pull-up resistors to any V CC that meets the Stratix high-level input voltage (V IH )specification.(2) The nCEO pins are left unconnected when configuring the same data into multiple Stratix or Stratix GX devices.fFor more information on configuring multiple Altera devices in the sameconfiguration chain, see the Configuring Mixed Altera FPGA Chainschapter in the Configuration Handbook, Volume 2.11–28 Altera CorporationStratix Device Handbook, Volume 2 July 2005