Configuration Handbook - Kamami.pl

Configuring Cyclone FPGAsFigure 13–14. PS Configuration Circuit with a Download Cable10 kΩ(3)V CC (1)V CC (1)(3)10 kΩV CC (1)V CC (1)V CC (1)Cyclone Device10 kΩ 10 kΩ 10 kΩV CC (4)GNDMSEL0MSEL1nCEDCLKDATA0nCONFIGCONF_DONEnSTATUSnCEON.C.Pin 110-Pin Male Header(PS Mode)V CCGNDVIO (2)ShieldGNDNotes to Figure 13–14:(1) You should connect the pull-up resistor to the same supply voltage as the MasterBlaster (VIO pin) or ByteBlasterMVcable.(2) Pin 6 of the header is a V IO reference voltage for the MasterBlaster output driver. V IO should match the device’sV CCIO . This pin is a no-connect pin for the ByteBlasterMV header.(3) The pull-up resistors on DATA0 and DCLK are only needed if the download cable is the only configuration schemeused on your board. This is to ensure that DATA0 and DCLK are not left floating after configuration. For example, ifyou are also using a configuration device, the pull-up resistors on DATA0 and DCLK are not needed.(4) Connect MSEL0 to the V CC supply voltage of the I/O bank it resides in.You can use the download cable to configure multiple Cyclone FPGAs byconnecting each device’s nCEO pin to the subsequent device’s nCE pin.All other configuration pins are connected to each device in the chain.Because all CONF_DONE pins are tied together, all devices in the chaininitialize and enter user mode at the same time. In addition, because thenSTATUS pins are tied together, the entire chain halts configuration if anydevice detects an error. In this situation, the Quartus II software mustrestart configuration; the Auto-Restart Configuration on Frame Erroroption does not affect the configuration cycle. Figure 13–15 shows how toconfigure multiple Cyclone FPGAs with a ByteBlaster II, MasterBlaster,or ByteBlasterMV cable.Altera Corporation 13–25January 2007 Cyclone Device Handbook, Volume 1