Configuration Handbook - Kamami.pl

Fast Passive Parallel ConfigurationFast PassiveParallelConfigurationFast Passive Parallel (FPP) configuration in APEX II devices is designedto meet the continuously increasing demand for faster configurationtimes. APEX II devices are designed with the capability of receiving bytewideconfiguration data per clock cycle, and guarantee a configurationtime of less than 100 ms with a 66-MHz configuration clock.FPP configuration of APEX II devices can be performed using an Alteraenhanced configuration device or an intelligent host, such as amicroprocessor.FPP Configuration Using an Enhanced Configuration DeviceIn the FPP configuration scheme, an enhanced configuration device sendsa byte of configuration data every DCLK cycle to the APEX II device.Configuration data is stored in the configuration device. Figure 6–16shows the configuration interface connections between the APEX IIdevice and the enhanced configuration device for single deviceconfiguration.1 The figures in this chapter only show the configuration-relatedpins and the configuration pin connections between theconfiguration device and the FPGA.fFor more information on the enhanced configuration device and flashinterface pins, such as PGM[2..0], EXCLK, PORSEL, A[20..0], andDQ[15..0], refer to the Enhanced Configuration Devices (EPC4, EPC8, &EPC16) Data Sheet in the Configuration Handbook.6–30 Altera CorporationConfiguration Handbook, Volume 1 August 2005