Configuration Handbook - Kamami.pl

Configuration SchemesFigure 13–13. Multi-Device PS Configuration Using Cascaded EPC2 or EPC1 DevicesV CC (1)(1) V CC (1)(3) 10 kΩ10 kΩ(2)10 kΩ (3)V CCV CC DCLKDCLKDCLKVDATA0CCDATA0DATAEPC2 or EPC1Cyclone Device 2Cyclone Device 1Device 1nSTATUSnSTATUSOE (3)MSEL1 CONF_DONEMSEL1 CONF_DONEnCS (3) nCASCMSEL0nCONFIGMSEL0nCONFIGnINIT_CONF (2)EPC2 or EPC1Device 2DCLKDATAnCSOEnINIT_CONFN.C.nCEOnCEnCEOnCEGNDGNDGNDNotes to Figure 13–13:(1) The pull-up resistor should be connected to the same supply voltage as the configuration device.(2) The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-upresistor that is always active, meaning an external pull-up resistor should not be used on the nINIT_CONFnCONFIGline. The nINIT_CONF pin does not need to be connected if its function is not used. If nINIT_CONF isnot used or not available (such as on EPC1 devices), nCONFIG must be pulled to V CC either directly or through aresistor.(3) The enhanced configuration devices' and EPC2 devices’ OE and nCS pins have internal programmable pull-upresistors. External 10-kΩ pull-up resistors should be used. To turn off the internal pull-up resistors, check theDisable nCS and OE pull-ups on configuration device option when generating programming files.PS Configuration Using a Download CableUsing a download cable in PS configuration, an intelligent host (forexample, your PC) transfers data from a storage device (for example,your hard drive) to the Cyclone FPGA through a USB Blaster,ByteBlaster II, MasterBlaster, or ByteBlasterMV cable. To initiateconfiguration in this scheme, the download cable generates a low-to-hightransition on the nCONFIG pin. The programming hardware then sendsthe configuration data one bit at a time on the device’s DATA0 pin. Thedata is clocked into the target device using DCLK until the CONF_DONEgoes high.When using programming hardware for the Cyclone FPGA, turning onthe Auto-Restart Configuration on Frame Error option does not affectthe configuration cycle because the Quartus II software must restartconfiguration when an error occurs. Figure 13–14 shows the PSconfiguration setup for the Cyclone FPGA using a USB Blaster,ByteBlaster II, MasterBlaster, or ByteBlasterMV cable.13–24 Altera CorporationCyclone Device Handbook, Volume 1 January 2007