Configuration Handbook - Kamami.pl

Configuring Stratix III Devicesf The TDO output is powered by the V CCPD power supply of I/O bank 1A.For recommendations on how to connect a JTAG chain with multiplevoltages across the devices in the chain, refer to the IEEE 1149.1 (JTAG)Boundary Scan Testing in Stratix III Devices Chapter of the Stratix III DeviceHandbook.Table 11–12. Dedicated JTAG PinsPin Name Pin Type DescriptionTDI Test data input Serial input pin for instructions as well as test and programming data. Data isshifted in the rising edge of TCK. If the JTAG interface is not required on theboard, you can disable the JTAG circuitry by connecting this pin to V CC .TDO Test data output Serial data output pin for instructions as well as test and programming data. Datais shifted out on the falling edge of TCK. The pin is tri-stated if data is not beingshifted out of the device. If the JTAG interface is not required on the board, youcan disable the JTAG circuitry by leaving this pin unconnected.TMS Test mode select Input pin that provides the control signal to determine the transitions of the TAPcontroller state machine. Transitions within the state machine occur on the risingedge of TCK. Therefore, you must set up TMS before the rising edge of TCK. TMSis evaluated on the rising edge of TCK. If the JTAG interface is not required onthe board, you can disable the JTAG circuitry by connecting this pin to V CC .TCK Test clock input The clock input to the BST circuitry. Some operations occur at the rising edgewhile others occur at the falling edge. If the JTAG interface is not required on theboard, you can disable the JTAG circuitry by connecting this pin to GND.TRSTTest reset input(optional)Active-low input to asynchronously reset the boundary-scan circuit. The TRSTpin is optional according to IEEE Std. 1149.1. If the JTAG interface is not requiredon the board, you can disable the JTAG circuitry by connecting this pin to GND.During JTAG configuration, you can download data to the device on thePCB through the USB Blaster, MasterBlaster, ByteBlaster II, orByteBlasterMV download cable. Configuring devices through a cable issimilar to programming devices in-system, except you should connect theTRST pin to V CC . This ensures that the TAP controller is not reset.Figure 11–29 shows JTAG configuration of a single Stratix III device.Altera Corporation 11–67May 2007 Stratix III Device Handbook, Volume 1