Configuration Handbook - Kamami.pl

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IntroductionTable 6–1. Configuration Options (Part 2 of 5)Device OptionEnable usersuppliedstart-upclock (CLKUSR)(Stratix series,Cyclone ® series,APEX TM II,APEX 20K, andMercury TM devicesonly).Option UsageThis option allows you toselect which clock source isused for initialization, eitherthe internal oscillator orexternal clocks provided onthe CLKUSR pin.Default Configuration(Option Off)The device’s internaloscillator (typically 10 MHz)supplies the initializationclock and the FPGA will takecare to provide itself withenough clock cycles forproper initialization.The CLKUSR pin is availableas a user I/O pin.Modified Configuration(Option On)The initialization clock mustbe provided on the CLKUSRpin. This clock cansynchronize the initializationof multiple devices. The clockshould be supplied when thelast data byte is transferred.Supplying a clock on CLKUSRwill not affect theconfiguration process.Enable usersuppliedstart-upclock (CLKUSR)(ACEX 1K, FLEX10K, and FLEX6000 devicesonly.)This option allows you toselect which clock source isused for initialization, eitherexternal clocks provided onthe CLKUSR pin or on theDCLK pin.In PS and PPS schemes, theinternal oscillator is disabled.Thus, external circuitry, suchas a configuration device ormicroprocessor, mustprovide the initialization clockon the DCLK pin.Programming files generatedby the Quartus II orMAX+PLUS II softwarealready have theseinitialization clock cyclesincluded in the file.In the PPA and PSAconfiguration schemes, thedevice’s internal oscillator(typically 10 MHz) suppliesthe initialization clock and theFPGA will take care toprovide itself with enoughclock cycles for properinitialization.The CLKUSR pin is availableas a user I/O pin.For more information on howmany clock cycles areneeded to properly initialize adevice, see the appropriatedevice family chapters.The initialization clock mustbe provided on the CLKUSRpin. This clock cansynchronize the initializationof multiple devices. The clockshould be supplied when thelast data byte is transferred.Supplying a clock on CLKUSRwill not affect theconfiguration process.For more information on howmany clock cycles areneeded to properly initialize adevice, see the appropriatedevice family chapters.6–6 Altera CorporationConfiguration Handbook, Volume 2 April 2007
Device Configuration OptionsTable 6–1. Configuration Options (Part 3 of 5)Device OptionEnable devicewidereset(DEV_CLRn)Option UsageEnables a single pin,DEV_CLRn, to reset alldevice registers.Default Configuration(Option Off)Chip-wide reset is notenabled. The DEV_CLRn pinis available as a user I/O pin.Modified Configuration(Option On)Chip-wide reset is enabledfor all registers in the device.All registers are clearedwhen the DEV_CLRn pin isdriven low.Enable devicewideoutput enable(DEV_OE)Enables a single pin,DEV_OE, to control all devicetri-states.Chip-wide output enable isnot enabled. The DEV_OE pinis available as a user I/O pin.The DEV_CLRn pin cannotbe used to clear only some ofthe registers; every deviceregister is affected by thisglobal signal.Chip-wide output enable isenabled for all device tristates.After configuration, alluser I/O pins are tri-statedwhen DEV_OE is low.The DEV_OE pin cannot beused to tri-state only some ofthe output pins; every outputpin is affected by this globalsignal.Altera Corporation 6–7April 2007 Configuration Handbook, Volume 2
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Configuration HandbookPreliminary I
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ContentsVolume I...................
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Altera FPGAsPreliminary Information
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IntroductionAll configuration schem
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Device Configuration Overview for P
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Selecting a Configuration SchemeSel
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Selecting a Configuration SchemePas
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IntroductionfFor information on enh
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Configuration FeaturesUse the data
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Configuration FeaturesStratix III d
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Configuration Features5. Select Add
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Configuration FeaturesV CCPGM PinsS
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Fast Passive Parallel Configuration
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Passive Serial ConfigurationPS Conf
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Passive Serial ConfigurationAn opti
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Passive Serial ConfigurationDCLK, D
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Passive Serial ConfigurationFigure
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Passive Serial Configuration1 To be
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Passive Serial Configuration1 If yo
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Passive Serial ConfigurationThe enh
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Passive Serial ConfigurationThe Qua
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Passive Serial Configuration1 You c
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Passive Serial Configurationoption
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Passive Serial ConfigurationIf you
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JTAG ConfigurationJTAGConfiguration
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JTAG ConfigurationFigure 11-29. JTA
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JTAG ConfigurationTable 11-13. Dedi
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JTAG ConfigurationAfter the first d
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Device Configuration PinsTable 11-1
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ConclusionConclusionDocumentRevisio
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Introduction1 For more information
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Configuration FeaturesTable 7-3. St
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Configuration Features1 When using
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Configuration Features6. Select the
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Configuration FeaturesV CCPD PinsSt
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Configuration Featuresthan 00X0 (MS
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Passive Serial ConfigurationTable 7
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Passive Serial ConfigurationfThe va
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Passive Serial Configurationpulled
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Passive Serial ConfigurationIf the
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Passive Serial Configurationconfigu
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Passive Serial ConfigurationUpon po
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Passive Serial ConfigurationIn addi
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Passive Parallel Asynchronous Confi
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JTAG ConfigurationJTAGConfiguration
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JTAG ConfigurationFigure 7-35. JTAG
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JTAG ConfigurationTable 7-20. Dedic
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ConclusionConclusionDocumentRevisio
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Device Configuration Overview■The
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Device Configuration Overviewrelate
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Configuration File SizeTDO & nCEO P
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Configuration SchemesPS Configurati
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Configuration SchemesFigure 11-2. S
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Configuration SchemesRestart Config
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Configuration SchemesTable 11-7 sho
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Configuration SchemesFigure 11-6. M
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Configuration SchemesTable 11-8. PS
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Configuration SchemesFPP Configurat
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Configuration SchemesDo not drive C
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Configuration Schemesdefault, the I
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Configuration SchemesFigure 11-13.
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Configuration SchemesTable 11-9. FP
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Configuration Schemesbe monitored,
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Configuration SchemesPPA Configurat
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Configuration SchemesTable 11-10 de
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Configuration SchemesDuring JTAG co
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Configuration SchemesJTAG-chain dev
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Cyclone II Configuration OverviewTa
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Configuration Data CompressionAltho
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PS ConfigurationPS ConfigurationYou
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PS ConfigurationConfiguration Stage
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PS Configurationdevice also pulls n
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PS ConfigurationYou must connect al
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PS ConfigurationPS Configuration Ti
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PS ConfigurationfAll information in
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PS ConfigurationUpon power-up, the
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PS ConfigurationnCONFIG is low and
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PS ConfigurationFigure 13-14. Multi
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PS ConfigurationnCONFIG low for at
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PS ConfigurationDATA3, you can leav
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PS ConfigurationPS Configuration Us
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PS ConfigurationIn addition, becaus
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PS Configurationthe five common sig
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JTAG ConfigurationA device operatin
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JTAG Configurationenables the progr
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JTAG ConfigurationFigure 13-23. JTA
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JTAG Configuration1 The Quartus II
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Device Configuration PinsReconfigur
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ConclusionTable 13-13 describes the
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Document Revision HistoryDocumentRe
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Device Configuration OverviewYou ca
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Data CompressionWhen you enable com
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Data CompressionCompression can als
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Configuration SchemesConfigurationS
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Configuration SchemesTable 13-9. Re
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Document Revision History13-52 Alte
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Choosing a Configuration DevicefFor
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Functional Description■■■■
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Functional DescriptionFigure 2-1. E
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Functional DescriptionIn addition t
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Functional DescriptionFast Passive
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Functional DescriptionThe configura
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Functional DescriptionTable 2-3 sum
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