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Configuration Handbook - Kamami.pl

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Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K DevicesTable 8–10. PS Timing Parameters for FLEX 10K Devices (Part 2 of 2)Symbol Parameter Min Max Unitsf MAX DCLK maximum frequency 16.7 MHzt CD2UM CONF_DONE high to user mode (2) 0.6 2 µsNotes to Table 8–10:(1) This value is obtainable if users do not delay configuration by extending the nSTATUS low pulse width.(2) The minimum and maximum numbers ap<strong>pl</strong>y only if DCLK is chosen as the clock source for starting up the device.If the clock source is CLKUSR, multi<strong>pl</strong>y the clock period by 10 to obtain this value.fDevice configuration options and how to create configuration files arediscussed further in Software Settings, chapters 6 and 7 in Volume 2 of the<strong>Configuration</strong> <strong>Handbook</strong>.Configuring Using the MicroBlaster DriverThe MicroBlaster TM software driver allows you to configure Altera’sFPGAs through the ByteBlasterMV cable in PS mode. The MicroBlastersoftware driver supports a RBF programming input file and is targetedfor embedded passive serial configuration. The source code is developedfor the Windows NT operating system, although you can customize it torun on other operating systems. For more information on theMicroBlaster software driver, go to the Altera web site(http://www.altera.com).PS <strong>Configuration</strong> Using a Download CableIn this section, the generic term “download cable” includes the AlteraUSB Blaster universal serial bus (USB) port download cable,MasterBlaster TM serial/USB communications cable, ByteBlaster TM IIparallel port download cable, and the ByteBlasterMV TM parallel portdownload cable.In PS configuration with a download cable, an intelligent host (e.g., a PC)transfers data from a storage device to the FPGA via the USB Blaster,MasterBlaster, ByteBlaster II, or ByteBlasterMV cable.Upon power-up, the Mercury, APEX 20K (2.5 V), ACEX 1K, or FLEX 10Kdevice goes through a POR for approximately 5 µs. During POR, thedevice resets and holds nSTATUS low, and tri-states all user I/O pins.Once the FPGA successfully exits POR, all user I/O pins are tri-stated.Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10KE devices haveweak pull-up resistors on the user I/O pins which are on before andduring configuration.Altera Corporation 8–29August 2005 <strong>Configuration</strong> <strong>Handbook</strong>, Volume 1

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