Configuration Handbook - Kamami.pl

Device Configuration PinsTable 11–16. Optional Configuration PinsPin Name User Mode Pin Type DescriptionCLKUSR N/A if option is on.I/O if option is off.Input Optional user-supplied clock input synchronizes theinitialization of one or more devices. Enable this pin byturning on the Enable user-supplied start-up clock(CLKUSR) option in the Quartus II software.INIT_DONE N/A if option is on.I/O if option is off.DEV_OEDEV_CLRnN/A if option is on.I/O if option is off.N/A if option is on.I/O if option is off.Output open-drainInputInputUse the Status pin to indicate when the device hasinitialized and is in user mode. When nCONFIG is lowand during the beginning of configuration, theINIT_DONE pin is tri-stated and pulled high due toan external 10-kΩ pull-up resistor. Once the option bitto enable INIT_DONE is programmed into the device(during the first frame of configuration data), theINIT_DONE pin will go low. When initialization iscomplete, the INIT_DONE pin is released and pulledhigh and the device enters user mode. Thus, themonitoring circuitry must be able to detect alow-to-high transition. This pin is enabled by turningon the Enable INIT_DONE output option in theQuartus II software.Optional pin that allows you to override all tri-states onthe device. When this pin is driven low, all I/O pins aretri-stated; when this pin is driven high, all I/O pinsbehave as programmed. Enable this pin by turning onthe Enable device-wide output enable (DEV_OE)option in the Quartus II software.Optional pin that allows you to override all clears onall device registers. When this pin is driven low, allregisters are cleared; when this pin is driven high, allregisters behave as programmed. This pin is enabledby turning on the Enable device-wide reset(DEV_CLRn) option in the Quartus II software.Table 11–17 describes the dedicated JTAG pins. JTAG pins must be keptstable before and during configuration to prevent accidental loading ofJTAG instructions. The TDI, TMS, and TRST have weak internal pull-upresistors while TCK has a weak internal pull-down resistor (typically25 kΩ). If you plan to use the SignalTap ® embedded logic array analyzer,you need to connect the JTAG pins of the Stratix III device to a JTAGheader on your board.11–82 Altera CorporationStratix III Device Handbook, Volume 1 May 2007