Configuration Handbook - Kamami.pl

Passive Serial ConfigurationTable 7–15. PS Timing Parameters for Stratix II & Stratix II GX Devices (Part 2 of 2) Note (1)Symbol Parameter Min Max Unitst CFG nCONFIG low pulse width 2 µst STATUS nSTATUS low pulse width 10 100 (2) µst CF2ST1 nCONFIG high to nSTATUS high 100 (2) µst CF2CK nCONFIG high to first rising edge on DCLK 100 µst ST2CK nSTATUS high to first rising edge of DCLK 2 µst DSU Data setup time before rising edge on DCLK 5 nst DH Data hold time after rising edge on DCLK 0 nst CH DCLK high time 4 nst CL DCLK low time 4 nst CLK DCLK period 10 nsf MAX DCLK frequency 100 MHzt R Input rise time 40 nst F Input fall time 40 nst CD2UM CONF_DONE high to user mode (3) 20 100 µst CD2CU CONF_DONE high to CLKUSR enabled 4 × maximumDCLK periodt CD2UMCCONF_DONE high to user mode withCLKUSR option ont CD2CU + (299 ×CLKUSR period)Notes to Table 7–15:(1) This information is preliminary.(2) This value is applicable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulsewidth.(3) The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for startingthe device.fDevice configuration options and how to create configuration files arediscussed further in Software Settings in volume 2 of the ConfigurationHandbook.An example PS design that uses a MAX II device as the external host forconfiguration will be available when devices are available.PS Configuration Using a MicroprocessorIn the PS configuration scheme, a microprocessor can control the transferof configuration data from a storage device, such as flash memory, to thetarget Stratix II or Stratix II GX device.7–54 Altera CorporationStratix II Device Handbook, Volume 2 May 2007