Configuration Handbook - Kamami.pl

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Configuring Cyclone II DevicesQuartus II programmer and a download cable. Figure 13–19 shows the PSconfiguration for Cyclone II devices using a USB-Blaster, MasterBlaster,ByteBlaster II or ByteBlasterMV cable.Figure 13–19. PS Configuration Using a USB-Blaster, MasterBlaster, ByteBlaster II or ByteBlasterMV CableV CC (1)(2)10 kΩV CC (1)V CC (1)V CC (1)V CC (1)10 kΩ(2)Cyclone II Device10 kΩ 10 kΩ 10 kΩV CCGNDCONF_DONEnSTATUSMSEL0MSEL1nCEnCEO N.C. (4)DCLKDATA0nCONFIGUSB-Blaster, ByteBlaster II,MasterBlaster,or ByteBlasterMV10-Pin Male HeaderPin 1V CCGNDVIO (3)ShieldGNDNotes to Figure 13–19:(1) The pull-up resistor should be connected to the same supply voltage as the USB-Blaster, MasterBlaster (VIO pin),ByteBlaster II, or ByteBlasterMV cable.(2) The pull-up resistors on DATA0 and DCLK are only needed if the download cable is the only configuration schemeused on your board. This is to ensure that DATA0 and DCLK are not left floating after configuration. For example, ifyou are also using a configuration device, the pull-up resistors on DATA0 and DCLK are not needed.(3) Pin 6 of the header is a V IO reference voltage for the MasterBlaster output driver. V IO should match the device’sV CCIO . Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlasterMV,this pin is a no connect. In the USB-Blaster and ByteBlaster II, this pin is connected to nCE when it is used for ASprogramming, otherwise it is a no connect.(4) The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed other device’s nCE pin.You can use a download cable to configure multiple Cyclone II devices byconnecting each device’s nCEO pin to the subsequent device’s nCE pin.Connect the first Cyclone II device’s nCE pin to GND and connect itsnCEO pin to the nCE pin of the next device in the chain. Use an external10-kΩ pull-up resistor to pull the nCEO pin high to V CCIO when it feedsnext device’s nCE pin. Connect all other configuration pins (nCONFIG,nSTATUS, DCLK, DATA0, and CONF_DONE) on every device in the chaintogether. Because all CONF_DONE pins are connected, all devices in thechain initialize and enter user mode at the same time.Altera Corporation 13–49February 2007 Cyclone II Device Handbook, Volume 1
PS ConfigurationIn addition, because the nSTATUS pins are connected, all the Cyclone IIdevices in the chain stop configuration if any device detects an error. Ifthis happens, you must manually restart configuration in the Quartus IIsoftware.Figure 13–20 shows how to configure multiple Cyclone II devices with adownload cable.13–50 Altera CorporationCyclone II Device Handbook, Volume 1 February 2007
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Configuration HandbookPreliminary I
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ContentsVolume I...................
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Altera FPGAsPreliminary Information
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IntroductionAll configuration schem
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Device Configuration Overview for P
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Selecting a Configuration SchemeSel
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Selecting a Configuration SchemePas
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IntroductionfFor information on enh
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Configuration FeaturesUse the data
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Configuration FeaturesStratix III d
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Configuration Features5. Select Add
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Configuration FeaturesV CCPGM PinsS
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Fast Passive Parallel Configuration
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Fast Active Serial Configuration (S
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Passive Serial ConfigurationPS Conf
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Passive Serial ConfigurationAn opti
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Passive Serial ConfigurationDCLK, D
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Passive Serial ConfigurationFigure
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Passive Serial Configuration1 To be
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Passive Serial Configuration1 If yo
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Passive Serial ConfigurationThe enh
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Passive Serial ConfigurationThe Qua
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Passive Serial Configuration1 You c
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Passive Serial Configurationoption
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Passive Serial ConfigurationIf you
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JTAG ConfigurationJTAGConfiguration
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JTAG ConfigurationFigure 11-29. JTA
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JTAG ConfigurationTable 11-13. Dedi
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JTAG ConfigurationAfter the first d
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Device Configuration PinsTable 11-1
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ConclusionConclusionDocumentRevisio
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Introduction1 For more information
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Configuration FeaturesTable 7-3. St
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Configuration Features1 When using
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Configuration Features6. Select the
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Configuration FeaturesV CCPD PinsSt
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Configuration Featuresthan 00X0 (MS
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Passive Serial ConfigurationTable 7
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Passive Serial ConfigurationfThe va
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Passive Serial Configurationpulled
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Passive Serial ConfigurationIf the
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Passive Serial Configurationsoftwar
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Passive Serial Configurationconfigu
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Passive Serial ConfigurationUpon po
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Passive Serial ConfigurationIn addi
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Passive Parallel Asynchronous Confi
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JTAG ConfigurationJTAGConfiguration
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JTAG ConfigurationFigure 7-35. JTAG
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JTAG ConfigurationTable 7-20. Dedic
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Device Configuration PinsDeviceConf
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ConclusionConclusionDocumentRevisio
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Device Configuration Overview■The
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Device Configuration Overviewrelate
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Configuration File SizeTDO & nCEO P
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Configuration SchemesPS Configurati
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Configuration SchemesFigure 11-2. S
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Configuration SchemesRestart Config
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Configuration SchemesTable 11-7 sho
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Configuration SchemesFigure 11-6. M
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Configuration SchemesTable 11-8. PS
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Configuration SchemesFPP Configurat
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Configuration SchemesDo not drive C
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Configuration Schemesdefault, the I
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Configuration SchemesFigure 11-13.
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Configuration SchemesTable 11-9. FP
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Configuration Schemesbe monitored,
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Configuration SchemesPPA Configurat
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Configuration SchemesTable 11-10 de
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Configuration SchemesDuring JTAG co
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Configuration SchemesJTAG-chain dev
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Configuration SchemesTable 11-14. R
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Passive Serial Configurationinterna
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JTAG ConfigurationTable 6-6. PPA Ti
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JTAG ConfigurationDuring JTAG confi
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JTAG ConfigurationFigure 6-30. JTAG
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Device Configuration PinsfFor more
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Device Configuration PinsTable 6-9.
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Device Configuration PinsJTAG pins
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IntroductionTable 7-2 shows the app
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Passive Serial Configuration1 V CCI
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Passive Serial ConfigurationWhen CO
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Passive Serial ConfigurationThe fol
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Choosing a Configuration DevicefFor
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Functional Description■■■■
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Functional DescriptionFigure 2-1. E
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Functional DescriptionIn addition t
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Functional DescriptionFast Passive
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Functional DescriptionThe configura
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Functional DescriptionTable 2-3 sum
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Configuring Mixed Altera FPGA Chain
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