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Configuration Handbook - Kamami.pl

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Fast Passive Parallel <strong>Configuration</strong>Figure 6–22. Multi<strong>pl</strong>e-Device FPP <strong>Configuration</strong> Using a Microprocessor When Both FPGAs Receive theSame DataMemoryADDRDATA[7..0]V CC (1)V CC (1)1 kΩ 1 kΩAPEX II DeviceV CCAPEX II DeviceV CCMicroprocessorGNDMSEL1MSEL0CONF_DONEnSTATUSnCEDATA[7..0]nCEOGNDN.C. (2)GNDMSEL1MSEL0CONF_DONEnSTATUSnCEDATA[7..0]nCEOGNDN.C. (2)nCONFIGDCLKnCONFIGDCLKNotes to Figure 6–22:(1) The pull-up resistor should be connected to a sup<strong>pl</strong>y that provides an acceptable input signal for all devices in thechain.(2) The nCEO pins of both devices are left unconnected when configuring the same configuration data into multi<strong>pl</strong>edevices.You can use a single configuration chain to configure APEX II deviceswith other Altera devices that support FPP configuration, such as Stratix.To ensure that all devices in the chain com<strong>pl</strong>ete configuration at the sametime or that an error flagged by one device initiates reconfiguration in alldevices, all of the device CONF_DONE and nSTATUS pins must be tiedtogether.fFor more information on configuring multi<strong>pl</strong>e Altera devices in the sameconfiguration chain, refer to Configuring Mixed Altera FPGA Chains in the<strong>Configuration</strong> <strong>Handbook</strong>.Figure 6–23 shows the timing waveform for the FPP configurationscheme using a microprocessor.6–44 Altera Corporation<strong>Configuration</strong> <strong>Handbook</strong>, Volume 1 August 2005

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