Configuration Handbook - Kamami.pl

Configuring APEX II DevicesfFor more information about configuring multiple Altera devices in thesame configuration chain, refer to Configuring Mixed Altera FPGA Chainsin the Configuration Handbook.The Quartus II software verifies successful JTAG configuration uponcompletion. At the end of configuration, the software checks the state ofCONF_DONE through the JTAG port. If CONF_DONE is not high, theQuartus II software indicates that configuration has failed. If CONF_DONEis high, the software indicates that configuration was successful. WhenQuartus II generates a JAM file for a multi-device chain, it containsinstructions so that all the devices in the chain will be initialized at thesame time.Figure 6–31 shows JTAG configuration of an APEX II FPGA with amicroprocessor.Figure 6–31. JTAG Configuration of a Single Device Using a MicroprocessorMemoryAPEX II DeviceADDR DATAMicroprocessorV CCTRSTTDITCKTMSTDO(3) nCEnCEOnCONFIGMSEL0MSEL1nSTATUSCONF_DONEGNDN.C. V CC (1)V CC (1)(2)1 kΩ(2) 1 kΩ(2)Notes to Figure 6–31:(1) The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in thechain.(2) Connect the nCONFIG, MSEL1, and MSEL0 pins to support a non-JTAG configuration scheme. If your design onlyuses JTAG configuration, connect the nCONFIG pin to V CC and the MSEL1 and MSEL0 pins to ground.(3) nCE must be connected to GND or driven low for successful JTAG configuration.Jam STAPLJam STAPL, JEDEC standard JESD-71, is a standard file format for insystemprogrammability (ISP) purposes. Jam STAPL supportsprogramming or configuration of programmable devices and testing ofelectronic systems, using the IEEE 1149.1 JTAG interface. Jam STAPL is afreely licensed open standard.The Jam Player provides an interface for manipulating the IEEE Std.1149.1 JTAG TAP state machine.Altera Corporation 6–61August 2005 Configuration Handbook, Volume 1