Configuration Handbook - Kamami.pl

Passive Serial ConfigurationAn optional INIT_DONE pin is available, which signals the end ofinitialization and the start of user-mode with a low-to-high transition.The Enable INIT_DONE output option is available in the Quartus IIsoftware from the General tab of the Device & Pin Options dialog box.If the INIT_DONE pin is used, it will be high due to an external 1-kΩ pullupresistor when nCONFIG is low and during the beginning ofconfiguration. Once the option bit to enable INIT_DONE is programmedinto the device (during the first frame of configuration data), theINIT_DONE pin goes low. When initialization is complete, theINIT_DONE pin is released and pulled high. This low-to-high transitionsignals that the FPGA has entered user mode. In user-mode, the user I/Opins will no longer have weak pull-up resistors and will function asassigned in your design. The enhanced configuration device drives DCLKlow and DATA high at the end of configuration.If an error occurs during configuration, the FPGA drives its nSTATUS pinlow, resetting itself internally. Since the nSTATUS pin is tied to OE, theconfiguration device will also be reset. If the Auto-Restart ConfigurationAfter Error option available in the Quartus II software from the Generaltab of the Device & Pin Options dialog box is turned on, the FPGAautomatically initiates reconfiguration if an error occurs. The APEX IIdevice will release its nSTATUS pin after a reset time-out period(maximum of 40 µs). When the nSTATUS pin is released and pulled highby a pull-up resistor, the configuration device reconfigures the chain. Ifthis option is turned off, the external system must monitor nSTATUS forerrors and then pulse nCONFIG low for at least 8 µs to restartconfiguration. The external system can pulse nCONFIG if nCONFIG isunder system control rather than tied to V CC .In addition, if the configuration device sends all of its data and thendetects that CONF_DONE has not gone high, it recognizes that the FPGAhas not configured successfully. Enhanced configuration devices wait for64 DCLK cycles after the last configuration bit was sent for CONF_DONE toreach a high state. EPC2 devices wait for 16 DCLK cycles. In this case, theconfiguration device pulls its OE pin low, which in turn drives the targetdevice’s nSTATUS pin low. If the Auto-Restart Configuration After Erroroption is set in the software, the target device resets and then releases itsnSTATUS pin after a reset time-out period (maximum of 40 µs). WhennSTATUS returns high, the configuration device tries to reconfigure theFPGA.6–6 Altera CorporationConfiguration Handbook, Volume 1 August 2005