Configuration Handbook - Kamami.pl

Configuration SchemesFPP Configuration Using an Enhanced Configuration DeviceWhen using FPP with an enhanced configuration device, it supplies datain a byte-wide fashion to the Stratix or Stratix GX device every DCLKcycle. See Figure 11–10.Figure 11–10. FPP Configuration Using Enhanced Configuration DevicesStratix orStratix GX DeviceDCLKDATA[7..0]nSTATUSCONF_DONEnCONFIGMSEL2nCEOMSEL1MSEL0nCEN.C.V CC (1) V CC (1)10 kΩ(2)10 kΩ(2)EnhancedConfigurationDeviceDCLKDATA[7..0]OE (2)nCS (2)nINIT_CONF (3)GNDGNDNotes to Figure 11–10:(1) The pull-up resistors should be connected to the same supply voltage as theconfiguration device.(2) The enhanced configuration devices and EPC2 devices have internalprogrammable pull-ups on OE and nCS. You should only use the internal pull-upsof the configuration device if the nSTATUS and CONF_DONE signals are pulled upto 3.3 V or 2.5 V (not 1.8 V or 1.5 V). If external pull-ups are used, they should be10 kΩ.(3) The nINIT_CONF pin is available on EPC16, EPC8, EPC4, and EPC2 devices. IfnINIT_CONF is not used, nCONFIG must be pulled to V CC through a resistor. ThenINIT_CONF pin has an internal pull-up resistor that is always active in EPC16,EPC8, EPC4, and EPC2 devices. These devices do not need an external pull-upresistor on the nINIT_CONF pin.In the enhanced configuration device scheme, nCONFIG is tied tonINIT_CONF. On power up, the target Stratix or Stratix GX device sensesthe low-to-high transition on nCONFIG and initiates configuration. Thetarget Stratix or Stratix GX device then drives the open-drain CONF_DONEpin low, which in-turn drives the enhanced configuration device’s nCSpin low.Before configuration starts, there is a 2-ms POR delay if the PORSEL pinis connected to V CC in the enhanced configuration device. If the PORSELpin is connected to ground, the POR delay is 100 ms. When each devicedetermines that its power is stable, it releases its nSTATUS or OE pin.Because the enhanced configuration device’s OE pin is connected to thetarget Stratix or Stratix GX device’s nSTATUS pin, configuration isdelayed until both the nSTATUS and OE pins are released by each device.The nSTATUS and OE pins are pulled up by a resistor on their respective11–22 Altera CorporationStratix Device Handbook, Volume 2 July 2005