Configuration Handbook - Kamami.pl

Passive Serial ConfigurationFigure 6–9. Single Device PS Configuration Using a MicroprocessorMemoryADDR DATA0(1) VCC VCC (1)1 kΩ 1 kΩAPEX II DeviceMicroprocessorGNDMSEL1MSEL0CONF_DONEnSTATUSnCEnCEOGNDN.C.DATA0nCONFIGDCLKNote to Figure 6–9:(1) Connect the pull-up resistor to a supply that provides an acceptable input signalfor the device.Upon power-up, the APEX II device goes through a POR forapproximately 5 µs. During POR, the device resets and holds nSTATUSlow, and tri-states all user I/O pins. Once the FPGA successfully exitsPOR, all user I/O pins are tri-stated. APEX II devices have weak pull-upresistors on the user I/O pins which are on before and duringconfiguration.fThe value of the weak pull-up resistors on the I/O pins that are on beforeand during configuration can be found in the Operating Conditions tableof the APEX II Programmable Logic Device Family Data Sheet.The configuration cycle consists of three stages: reset, configuration, andinitialization. While nCONFIG or nSTATUS are low, the device is in reset.To initiate configuration, the microprocessor must generate a low-to-hightransition on the nCONFIG pin.1 VCCINT and VCCIO pins on the banks where the configurationand JTAG pins reside need to be fully powered to theappropriate voltage levels in order to begin the configurationprocess.When nCONFIG goes high, the device comes out of reset and releases theopen-drain nSTATUS pin, which is then pulled high by an external 1-kΩpull-up resistor. Once nSTATUS is released, the FPGA is ready to receiveconfiguration data and the configuration stage begins. When nSTATUS ispulled high, the microprocessor should place the configuration data onebit at a time on the DATA0 pin. The least significant bit (LSB) of each databyte must be sent first.6–18 Altera CorporationConfiguration Handbook, Volume 1 August 2005