Configuration Handbook - Kamami.pl

Configuring Stratix & Stratix GX DevicesFigure 11–23. Embedded System Block DiagramEmbedded Systemto/from ByteBlasterMVTDITMSTCKTDOInterfaceLogic(Optional)TDIEmbeddedProcessorControld[7..0]adr[19..0]208420820Controld[3..0]adr[19..0]Controld[7..0]adr[19..0]TMSTCKTDOEPROM orSystemMemoryTMSTCKTMSTCKTDITDOTDITDOAny JTAGDeviceMAX ® 9000,MAX 9000A,MAX 7000S,MAX 7000A,MAX 7000AE,or MAX 3000DeviceV CC V CC V CCTMSTCKTDITRSTnSTATUSCONF_DONEnCONFIGMSEL0MSEL1TDO nCETDIGND10 kΩ10 kΩAny Cyclone,FLEX 10K,FLEX 10KA,FLEX10KE,APEX 20K,or APEX 20KEDeviceTMSTCKMSEL1MSEL0(1)(1)(2)(2)(1)DATA0DCLKnCONFIGTDOCyclone FPGANotes to Figure 11–23:(1) Connect the nCONFIG, MSEL2, MSEL1, and MSEL0 pins to support a non-JTAG configuration scheme. If your designonly uses JTAG configuration, connect the nCONFIG pin to V CC and the MSEL2, MSEL1, and MSEL0 pins to ground.(2) Pull DATA0 and DCLK to either high or low.Both JTAG connection methods should include space for theMasterBlaster or ByteBlasterMV header connection. The header is usefulduring prototyping because it allows you to verify or modify the Stratixor Stratix GX device’s contents. During production, you can remove theheader to save cost.Altera Corporation 11–43July 2005 Stratix Device Handbook, Volume 2