Configuration Handbook - Kamami.pl

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Configuring Stratix III Devices1 You cannot cascade enhanced configuration devices.When performing multi-device configuration, you must generate theconfiguration device's POF from each project's SOF. You can combinemultiple SOFs using the Convert Programming Files window in theQuartus II software.fFor more information on how to create configuration files formulti-device configuration chains, refer to the Software Settings chapterof the Configuration Handbook.In multi-device PS configuration, the first device's nCE pin is connectedto GND while its nCEO pin is connected to nCE of the next device in thechain. The last device's nCE input comes from the previous device, whileits nCEO pin is left floating. After the first device completes configurationin a multi-device configuration chain, its nCEO pin drives low to activatethe second device's nCE pin, prompting the second device to beginconfiguration. All other configuration pins (nCONFIG, nSTATUS, DCLK,DATA0, and CONF_DONE) are connected to every device in the chain.Configuration signals can require buffering to ensure signal integrity andprevent clock skew problems. Ensure that the DCLK and DATA lines arebuffered for every fourth device.When configuring multiple devices, configuration does not begin until alldevices release their OE or nSTATUS pins. Similarly, since all deviceCONF_DONE pins are tied together, all devices initialize and enter usermode at the same time.Since all nSTATUS and CONF_DONE pins are tied together, if any devicedetects an error, configuration stops for the entire chain and you mustreconfigure the entire chain. For example, if the first device flags an erroron nSTATUS, it resets the chain by pulling its nSTATUS pin low. This lowsignal drives the OE pin low on the enhanced configuration device anddrives nSTATUS low on all devices, causing them to enter a reset state.This behavior is similar to a single device detecting an error.If the Auto-restart configuration after error option is turned on, thedevices will automatically initiate reconfiguration if an error occurs. Thedevices will release their nSTATUS pins after a reset time-out period(maximum of 100 ms). When all the nSTATUS pins are released andpulled high, the configuration device tries to reconfigure the chain. If theAuto-restart configuration after error option is turned off, the externalsystem must monitor nSTATUS for errors and then pulse nCONFIG lowfor at least 2 ms to restart configuration. The external system can pulsenCONFIG if nCONFIG is under system control rather than tied to V CC .Altera Corporation 11–55May 2007 Stratix III Device Handbook, Volume 1
Passive Serial ConfigurationThe enhanced configuration devices also support parallel configurationof up to eight devices. The n-bit (= 1, 2, 4, or 8) PS configuration modeallows enhanced configuration devices to concurrently configure devicesor a chain of devices. In addition, these devices do not have to be the samedevice family or density as they can be any combination of Altera devices.An individual enhanced configuration device DATA line is available foreach targeted device. Each DATA line can also feed a daisy chain ofdevices. Figure 11–23 shows how to concurrently configure multipledevices using an enhanced configuration device.11–56 Altera CorporationStratix III Device Handbook, Volume 1 May 2007
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Configuration HandbookPreliminary I
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ContentsVolume I...................
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Altera FPGAsPreliminary Information
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IntroductionAll configuration schem
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Device Configuration Overview for P
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Selecting a Configuration SchemeSel
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Selecting a Configuration SchemePas
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IntroductionfFor information on enh
Page 17 and 18: Configuration FeaturesUse the data
Page 19 and 20: Configuration FeaturesStratix III d
Page 21 and 22: Configuration Features5. Select Add
Page 23 and 24: Configuration FeaturesV CCPGM PinsS
Page 25 and 26: Fast Passive Parallel Configuration
Page 43 and 44: Fast Active Serial Configuration (S
Page 55 and 56: Passive Serial ConfigurationPS Conf
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Page 81 and 82: JTAG ConfigurationFigure 11-29. JTA
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Page 87 and 88: Device Configuration PinsTable 11-1
Page 97 and 98: ConclusionConclusionDocumentRevisio
Page 99 and 100: Introduction1 For more information
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Fast Passive Parallel Configuration
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Active Serial Configuration (Serial
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Passive Serial ConfigurationTable 7
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Passive Serial ConfigurationfThe va
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Passive Serial Configurationpulled
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Passive Serial ConfigurationIf the
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Passive Serial Configurationsoftwar
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Passive Serial ConfigurationFigure
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Passive Serial Configurationconfigu
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Passive Serial ConfigurationUpon po
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Passive Parallel Asynchronous Confi
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JTAG ConfigurationJTAGConfiguration
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JTAG ConfigurationFigure 7-35. JTAG
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JTAG ConfigurationTable 7-20. Dedic
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JTAG ConfigurationAfter the first d
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Device Configuration PinsDeviceConf
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Device Configuration PinsTable 7-22
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ConclusionConclusionDocumentRevisio
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Device Configuration Overview■The
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Device Configuration Overviewrelate
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Configuration File SizeTDO & nCEO P
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Configuration SchemesPS Configurati
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Configuration SchemesFigure 11-2. S
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Configuration SchemesRestart Config
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Configuration SchemesTable 11-7 sho
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Configuration SchemesFigure 11-6. M
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Configuration SchemesTable 11-8. PS
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Configuration SchemesFPP Configurat
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Configuration SchemesDo not drive C
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Configuration Schemesdefault, the I
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Configuration SchemesFigure 11-13.
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Configuration SchemesTable 11-9. FP
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Configuration Schemesbe monitored,
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Configuration SchemesPPA Configurat
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Configuration SchemesTable 11-10 de
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Configuration SchemesDuring JTAG co
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Configuration SchemesJTAG-chain dev
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Configuration SchemesfFor more info
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Configuration SchemesProgram FlowTh
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Configuration Schemessend JTAG data
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Configuration SchemesTable 11-14. R
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Cyclone II Configuration OverviewTa
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Configuration Data CompressionAltho
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PS ConfigurationPS ConfigurationYou
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PS ConfigurationConfiguration Stage
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PS Configurationdevice also pulls n
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PS ConfigurationYou must connect al
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PS ConfigurationPS Configuration Ti
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PS ConfigurationfAll information in
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PS ConfigurationUpon power-up, the
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PS ConfigurationnCONFIG is low and
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PS ConfigurationFigure 13-14. Multi
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PS ConfigurationnCONFIG low for at
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PS ConfigurationDATA3, you can leav
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PS ConfigurationPS Configuration Us
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PS ConfigurationIn addition, becaus
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PS Configurationthe five common sig
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JTAG ConfigurationA device operatin
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JTAG Configurationenables the progr
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JTAG ConfigurationFigure 13-23. JTA
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JTAG Configuration1 The Quartus II
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JTAG Configurationfeature. To use t
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Device Configuration PinsReconfigur
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ConclusionTable 13-13 describes the
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Document Revision HistoryDocumentRe
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Device Configuration OverviewYou ca
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Data CompressionWhen you enable com
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Data CompressionCompression can als
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Configuration SchemesConfigurationS
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Configuration Schemesinternal oscil
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Configuration SchemesFigure 13-6. C
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Configuration SchemesFigure 13-7. C
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Configuration SchemesASDI and nCS s
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Configuration SchemesFigure 13-18 s
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Configuration Schemesattempt JTAG c
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Configuration Schemes1 If V CCIO is
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Configuration Schemes1 Both JTAG co
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Configuration Schemessend JTAG data
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Configuration SchemesTable 13-9. Re
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Document Revision History13-52 Alte
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Passive Serial Configurationinterna
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JTAG ConfigurationTable 6-6. PPA Ti
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JTAG ConfigurationDuring JTAG confi
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JTAG ConfigurationFigure 6-30. JTAG
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Device Configuration PinsfFor more
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Device Configuration PinsTable 6-9.
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Device Configuration PinsJTAG pins
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IntroductionTable 7-2 shows the app
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Passive Serial Configuration1 V CCI
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JTAG ConfigurationTable 7-6. PPA Ti
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JTAG Configurationprogramming devic
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JTAG ConfigurationJTAG-chain device
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APEX 20KE Power SequencingThese gui
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APEX 20KE Power SequencingUse these
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JTAG ConfigurationMercury, APEX 20K
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JTAG ConfigurationOther Altera devi
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Device Configuration Pins8-70 Alter
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FPGA Configuration DevicesPrelimina
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Choosing a Configuration DevicefFor
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1-4 Altera CorporationConfiguration
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Functional Description■■■■
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Functional DescriptionFigure 2-1. E
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Functional DescriptionIn addition t
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Functional DescriptionFast Passive
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Functional DescriptionThe configura
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Functional DescriptionTable 2-3 sum
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Enhanced Configuration Devices (EPC
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5. Configuration Devices forSRAM-Ba
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Generating Configuration FilesYou c
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8. Configuring Mixed AlteraFPGA Cha
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Configuring Mixed Altera FPGA Chain
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Debugging Suggestions■■To check
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Debugging SuggestionsUsing JTAG Con
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Document Revision History11-8 Alter
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