Configuration Handbook - Kamami.pl

Configuring Stratix & Stratix GX DevicesFPP Configuration TimingFigure 11–15 shows FPP timing waveforms for configuring a Stratix orStratix GX device in FPP mode. Table 11–9 shows the FPP timingparameters for Stratix or Stratix GX devices.Figure 11–15. Timing Waveform for Configuring Devices in FPP Mode Note (1)t CFGt CF2ST1nCONFIGt CF2CKt STATUSnSTATUS (2)CONF_DONE (3)DCLKDATA[7..0}t CF2ST0 t CLKtt CH t CL CF2CD t ST2CKt DHByte 0 Byte 1 Byte 2 Byte 3 Byte nt DSUHigh-Z(4)(4)User ModeUser I/OUser ModeINIT_DONEt CD2UMNotes to Figure 11–15:(1) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, andCONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.(2) Upon power-up, the Stratix II device holds nSTATUS low for the time of the POR delay.(3) Upon power-up, before and during configuration, CONF_DONE is low.(4) DCLK should not be left floating after configuration. It should be driven high or low, whichever is convenient.DATA[] is available as user I/Os after configuration and the state of these pins depends on the dual-purpose pinsettings.Table 11–9. FPP Timing Parameters for Stratix & Stratix GX Devices (Part 1 of 2)Symbol Parameter Min Max Unitst CF2CK nCONFIG high to first rising edge on DCLK 40 µst DSU Data setup time before rising edge on DCLK 7 nst DH Data hold time after rising edge on DCLK 0 nst CFG nCONFIG low pulse width 40 µst CH DCLK high time 4 nst CL DCLK low time 4 nst CLK DCLK period 10 nsAltera Corporation 11–29July 2005 Stratix Device Handbook, Volume 2