Configuration Handbook - Kamami.pl

Timing InformationTable 4–20 defines the serial configuration device timing parameters forread operation.Table 4–20. Read Operation Parametersf RCLKSymbol Parameter Min Max UnitRead clock frequency (from20 MHzFPGA or embedded processor)for read bytes operationt CH DCLK high time 25 nst CL DCLK low time 25 nst ODIS Output disable time after read 15 nst nCLK2D Clock falling edge to data 15 nsFigure 4–18 shows the timing waveform for FPGA AS configurationscheme using a serial configuration device.Figure 4–18. AS Configuration Timingt CF2ST1nCONFIGnSTATUSCONF_DONEnCSODCLKASDORead Addresst CLt CHt Ht SUDATA0bit N bit N − 1bit 1 bit 0136 CyclesINIT_DONEUser I/OUser ModeTri-stated with internalpull-up resistor.4–34 Altera CorporationConfiguration Handbook, Volume 2 April 2007