Configuration Handbook - Kamami.pl

Configuring APEX II DevicesFigure 6–24. Single Device PPA Configuration Using a Microprocessor Note (1)Address DecoderADDRV CC(2)MemoryADDR DATA[7..0]1 kΩV CC(2)1 kΩAPEX II DeviceVCCMicroprocessorGNDnCS (1)CS (1)CONF_DONEnSTATUSnCEDATA[7..0]nWSnRSnCONFIGRDYnBSYMSEL1MSEL0nCEODCLKN.C.V CC (2)1 kΩNotes to Figure 6–24:(1) If not used, the CS pin can be connected to V CC directly. If not used, the nCS pin can be connected to GND directly.(2) The pull-up resistor should be connected to a supply that provides an acceptable input signal for the device.During PPA configuration, it is only required to use either the nCS or CSpin. Therefore, if only one chip-select input is used, the other must be tiedto the active state. For example, nCS can be tied to ground while CS istoggled to control configuration. The device’s nCS or CS pins can betoggled during PPA configuration if the design meets the specificationsset for t CSSU , t WSP , and t CSH listed in Table 6–6.Upon power-up, the APEX II device goes through a Power-On Reset(POR) for approximately 5 μs. During POR, the device resets and holdsnSTATUS low, and tri-states all user I/O pins. Once the FPGAsuccessfully exits POR, all user I/O pins are tri-stated. APEX II deviceshave weak pull-up resistors on the user I/O pins which are on before andduring configuration.fThe value of the weak pull-up resistors on the I/O pins that are on beforeand during configuration can be found in the Operating Conditions tableof the APEX II Programmable Logic Device Family Data Sheet.Altera Corporation 6–47August 2005 Configuration Handbook, Volume 1