Configuration Handbook - Kamami.pl

Configuring APEX 20KE & APEX 20KC DevicesFigure 7–20. Single Device PPA Configuration Using a Microprocessor Note (1)Address DecoderADDRV CC(2)ADDRMemoryDATA[7..0]10 kΩV CC(2)10 kΩAPEX 20KE orAPEX 20KC DeviceVCCMicroprocessorGNDnCS (1)CS (1)CONF_DONEnSTATUSnCEDATA[7..0]nWSnRSnCONFIGRDYnBSYMSEL1MSEL0nCEODCLKN.C.V CC(2)10 kΩNotes to Figure 7–20:(1) If not used, the CS pin can be connected to V CC directly. If not used, the nCS pin can be connected to GND directly.(2) The pull-up resistor should be connected to a supply that provides an acceptable input signal for the device.During PPA configuration, it is only required to use either the nCS or CSpin. Therefore, if only one chip-select input is used, the other must be tiedto the active state. For example, nCS can be tied to ground while CS istoggled to control configuration. The device’s nCS or CS pins can betoggled during PPA configuration if the design meets the specificationsset for t CSSU , t WSP , and t CSH listed in Table 7–6.Upon power-up, the APEX 20KE or APEX 20KC device goes through aPower-On Reset (POR) for approximately 5 μs. During POR, the deviceresets and holds nSTATUS low, and tri-states all user I/O pins. Once theFPGA successfully exits POR, all user I/O pins are tri-stated. APEX 20KEand APEX 20KC devices have weak pull-up resistors on the user I/O pinswhich are on before and during configuration.fThe value of the weak pull-up resistors on the I/O pins that are on beforeand during configuration can be found in the Operating Conditions tableof the APEX 20K Programmable Logic Device Family Data Sheet orAPEX 20KC Programmable Logic Device Family Data Sheet.Altera Corporation 7–43August 2005 Configuration Handbook, Volume 1