Configuration Handbook - Kamami.pl

IEEE Std. 1149.1 (JTAG) Boundary-ScanIEEE Std. 1149.1(JTAG)Boundary-ScanThe enhanced configuration device provides JTAG BST circuitry thatcomplies with the IEEE Std. 1149.1-1990 specification. JTAG boundaryscantesting can be performed before or after configuration, but notduring configuration.Figure 2–6 shows the timing requirements for the JTAG signals.Figure 2–6. JTAG Timing WaveformsTMSTDIt JCPt JCHt JCLt JPSUTCKt JPZX t JPCOt JPHt JPXZTDOSignalto beCapturedSignalto beDrivent JSZXt JSSU t JSHt JSCO t JSXZTable 2–11 shows the timing parameters and values for the enhancedconfiguration device.Table 2–11. JTAG Timing Parameters & Values (Part 1 of 2)Symbol Parameter Min Max Unitt JCP TCK clock period 100 nst JCH TCK clock high time 50 nst JCL TCK clock low time 50 nst JPSU JTAG port setup time 20 nst JPH JTAG port hold time 45 nst JPCO JTAG port clock output 25 nst JPZX JTAG port high impedance to valid output 25 nst JPXZ JTAG port valid output to high impedance 25 nst JSSU Capture register setup time 20 ns2–30 Altera CorporationConfiguration Handbook, Volume 2 May 2007