Configuration Handbook - Kamami.pl

Device Configuration PinsTable 13–11. Dedicated Configuration Pins on the Cyclone II Device (Part 5 of 5)Pin NameUserModeDCLK N/A PS,ASConfigurationSchemePin TypeInput (PS)Output (AS)DescriptionIn PS configuration, DCLK is the clock input used toclock data from an external source into the targetdevice. Data is latched into the Cyclone II device onthe rising edge of DCLK.In AS mode, DCLK is an output from the Cyclone IIdevice that provides timing for the configurationinterface. In AS mode, DCLK has an internal pull-upthat is always active.After configuration, this pin is tri-stated. If you areusing a configuration device, it drives DCLK low afterconfiguration is complete. If your design uses acontrol host, drive DCLK either high or low. Togglingthis pin after configuration does not affect theconfigured device.The input buffer on this pin supports hysteresis usingSchmitt trigger circuitry.DATA0 N/A All Input This is the data input pin. In serial configurationmodes, bit-wide configuration data is presented to thetarget device on the DATA0 pin.In AS mode, DATA0 has an internal pull-up resistorthat is always active.After configuration, EPC1 and EPC1441 devicestri-state this pin, while enhanced configuration andEPC2 devices drive this pin high.The input buffer on this pin supports hysteresis usingSchmitt trigger circuitry.13–68 Altera CorporationCyclone II Device Handbook, Volume 1 February 2007