Configuration Handbook - Kamami.pl

Configuration FeaturesV CCPD PinsStratix II and Stratix II GX devices also offer a new power supply, V CCPD ,which must be connected to 3.3-V in order to power the 3.3-V/2.5-Vbuffer available on the configuration input pins and JTAG pins. V CCPDapplies to all the JTAG input pins (TCK, TMS, TDI, and TRST) and theconfiguration pins when VCCSEL is connected to ground. Refer toTable 7–5 for information on the pins affected by VCCSEL.1 V CCPD must ramp-up from 0-V to 3.3-V within 100 ms. If V CCPDis not ramped up within this specified time, your Stratix II orStratix II GX device will not configure successfully. If yoursystem does not allow for a V CCPD ramp-up time of 100 ms orless, you must hold nCONFIG low until all power supplies arestable.VCCSEL PinThe VCCSEL pin selects the type of input buffer used on configurationinput pins and it selects the POR trip point voltage level for V CCIO bank 3powered by VCCIO3 pins.1 For more information, refer to Table 7–24 on page 7–105.The configuration input pins and the PLL_ENA pin (Table 7–5) have adual buffer design. These pins have a 3.3-V/2.5-V input buffer and a1.8-V/1.5-V input buffer. The VCCSEL input pin selects which inputbuffer is used during configuration. The 3.3-V/2.5-V input buffer ispowered by V CCPD , while the 1.8-V/1.5-V input buffer is powered byV CCIO . After configuration, the dual-purpose configuration pins arepowered by the V CCIO pins of the bank in which they reside. Table 7–5shows the pins affected by VCCSEL.7–10 Altera CorporationStratix II Device Handbook, Volume 2 May 2007