Configuration Handbook - Kamami.pl

Device Configuration PinsTable 7–22 describes the dedicated configuration pins, which are requiredto be connected properly on your board for successful configuration.Some of these pins may not be required for your configuration schemes.Table 7–22. Dedicated Configuration Pins on the Stratix II & Stratix II GX Device (Part 1 of 10)Pin NameUser ModeConfigurationSchemePin TypeDescriptionV CCPD N/A All Power Dedicated power pin. This pin is used to powerthe I/O pre-drivers, the JTAG input pins, andthe configuration input pins that are affectedby the voltage level of VCCSEL.This pin must be connected to 3.3-V. V CCPDmust ramp-up from 0-V to 3.3-V within 100 ms.If V CCPD is not ramped up within this specifiedtime, your Stratix II or Stratix II GX device willnot configure successfully. If your system doesnot allow for a V CCPD ramp-up time of 100 msor less, you must hold nCONFIG low until allpower supplies are stable.VCCSEL N/A All Input Dedicated input that selects which input bufferis used on the PLL_ENA pin and theconfiguration input pins; nCONFIG, DCLK(when used as an input), nSTATUS (whenused as an input), CONF_DONE (when usedas an input), DEV_OE, DEV_CLRn,DATA[7..0], RUnLU, nCE, nWS, nRS, CS,nCS, and CLKUSR. The 3.3-V/2.5-V inputbuffer is powered by V CCPD , while the 1.8-V/1.5-V input buffer is powered by V CCIO .The VCCSEL input buffer has an internal 5-kΩpull-down resistor that is always active. TheVCCSEL input buffer is powered by V CCINT andmust be hardwired to V CCPD or ground. A logichigh selects the 1.8-V/1.5-V input buffer, and alogic low selects the 3.3-V/2.5-V input buffer.For more information, refer to the “VCCSELPin” section.7–94 Altera CorporationStratix II Device Handbook, Volume 2 May 2007