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Configuration Handbook - Kamami.pl

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Configuring Stratix III DevicesTable 11–17. Dedicated JTAG PinsPin Name User Mode Pin TypeDescriptionTDI N/A Input Serial input pin for instructions as well as test and programming data. Datais shifted in on the rising edge of TCK. The TDI pin is powered by the 2.5-V/ 3.0-V V CCPD sup<strong>pl</strong>y.If the JTAG interface is not required on the board, you can disable the JTAGcircuitry by connecting this pin to V CC .TDO N/A Output Serial data output pin for instructions as well as test and programming data.Data is shifted out on the falling edge of TCK. The pin is tri-stated if data isnot being shifted out of the device. The TDO pin is powered by V CCPD Forrecommendations on connecting a JTAG chain with multi<strong>pl</strong>e voltages acrossthe devices in the chain, refer to the chapter IEEE 1149.1 (JTAG) BoundaryScan Testing in Stratix III Devices chapter in volume 1 of the Stratix IIIDevice <strong>Handbook</strong>.If the JTAG interface is not required on the board, you can disable the JTAGcircuitry by leaving this pin unconnected.TMS N/A Input Input pin that provides the control signal to determine the transitions of theTAP controller state machine. Transitions within the state machine occur onthe rising edge of TCK. Therefore, TMS must be set up before the rising edgeof TCK. TMS is evaluated on the rising edge of TCK. The TMS pin is poweredby the 2.5-V / 3.0-V V CCPD .If the JTAG interface is not required on the board, you can disable the JTAGcircuitry by connecting this pin to V CC .TCK N/A Input The clock input to the BST circuitry. Some operations occur at the risingedge, while others occur at the falling edge. The TCK pin is powered by the2.5-V / 3.0-V V CCPD sup<strong>pl</strong>y.It is expected that the clock input waveform have a nominal 50% duty cycle.If the JTAG interface is not required on the board, you can disable the JTAGcircuitry by connecting TCK to GND.TRST N/A Input Active-low input to asynchronously reset the boundary-scan circuit. TheTRST pin is optional according to IEEE Std. 1149.1. The TRST pin ispowered by the 2.5-V / 3.0-V V CCPD sup<strong>pl</strong>y.You should hold TMS at 1 or you should keep TCK static while TRST ischanged from 0 to 1.If the JTAG interface is not required on the board, you can disable the JTAGcircuitry by connecting the TRST pin to GND.Altera Corporation 11–83May 2007 Stratix III Device <strong>Handbook</strong>, Volume 1

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