Configuration Handbook - Kamami.pl

Configuring Stratix & Stratix GX Devicesprobes and capture functional data while a device is operating normally.You can also use the JTAG circuitry to shift configuration data into thedevice.fFor more information on JTAG boundary-scan testing, see AN 39: IEEE1149.1 (JTAG) Boundary-Scan Testing in Altera Devices.To use the SignalTap ® II embedded logic analyzer, you need to connectthe JTAG pins of your Stratix device to a download cable header on yourPCB.fFor more information on SignalTap II, see the Design Debugging UsingSignalTap II Embedded Logic Analyzer chapter in the Quartus II Handbook,Volume 2.A device operating in JTAG mode uses four required pins, TDI, TDO, TMS,and TCK, and one optional pin, TRST. The four JTAG input pins (TDI,TMS, TCK and TRST) have weak, internal pull-up resistors, whose valuesrange from 20 to 40 kΩ. All other pins are tri-stated during JTAGconfiguration. Do not begin JTAG configuration until all otherconfiguration is complete. Table 11–11 shows each JTAG pin’s function.Table 11–11. JTAG Pin DescriptionsPin Description FunctionTDI Test data input Serial input pin for instructions as well as test and programming data. Data isshifted in on the rising edge of TCK. The VCCSEL pin controls the input bufferselection.TDO Test data output Serial data output pin for instructions as well as test and programming data. Datais shifted out on the falling edge of TCK. The pin is tri-stated if data is not beingshifted out of the device. The high level output voltage is determined by VCCIO.TMS Test mode select Input pin that provides the control signal to determine the transitions of the TestAccess Port (TAP) controller state machine. Transitions within the state machineoccur on the rising edge of TCK. Therefore, TMS must be set up before the risingedge of TCK. TMS is evaluated on the rising edge of TCK. The VCCSEL pincontrols the input buffer selection.TCK Test clock input The clock input to the BST circuitry. Some operations occur at the rising edge,while others occur at the falling edge. The VCCSEL pin controls the input bufferselection.TRST Test reset input(optional)Active-low input to asynchronously reset the boundary-scan circuit. The TRSTpin is optional according to IEEE Std. 1149.1. The VCCSEL pin controls the inputbuffer selection.Altera Corporation 11–37July 2005 Stratix Device Handbook, Volume 2