12.07.2015 Views

Configuration Handbook - Kamami.pl

Configuration Handbook - Kamami.pl

Configuration Handbook - Kamami.pl

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

JTAG <strong>Configuration</strong>JTAG<strong>Configuration</strong>fThe JTAG has developed a specification for boundary-scan testing. Thisboundary-scan test (BST) architecture offers the capability to efficientlytest components on PCBs with tight lead spacing. The BST architecturecan test pin connections without using physical test probes and capturefunctional data while a device is operating normally. The JTAG circuitrycan also be used to shift configuration data into the device. The Quartus IIsoftware automatically generates SOFs that can be used for JTAGconfiguration with a download cable in the Quartus II softwareprogrammer.For more information on JTAG boundary-scan testing, refer to thefollowing documents:■■IEEE 1149.1 (JTAG) Boundary-Scan Testing for Stratix II Devices chapterin volume 2 of the Stratix II Device <strong>Handbook</strong> or the Stratix II GXDevice <strong>Handbook</strong>Jam Programming & Testing Language SpecificationStratix II and Stratix II GX devices are designed such that JTAGinstructions have precedence over any device configuration modes.Therefore, JTAG configuration can take <strong>pl</strong>ace without waiting for otherconfiguration modes to com<strong>pl</strong>ete. For exam<strong>pl</strong>e, if you attempt JTAGconfiguration of Stratix II or Stratix II GX devices during PSconfiguration, PS configuration is terminated and JTAG configurationbegins.1 You cannot use the Stratix II and Stratix II GX decompression ordesign security features if you are configuring your Stratix II orStratix II GX device when using JTAG-based configuration.A device operating in JTAG mode uses four required pins, TDI, TDO, TMS,and TCK, and one optional pin, TRST. The TCK pin has an internal weakpull-down resistor, while the TDI, TMS, and TRST pins have weakinternal pull-up resistors (typically 25 kΩ). The TDO output pin ispowered by V CCIO in I/O bank 4. All of the JTAG input pins are poweredby the 3.3-V V CCPD pin. All user I/O pins are tri-stated during JTAGconfiguration. Table 7–19 ex<strong>pl</strong>ains each JTAG pin’s function.7–84 Altera CorporationStratix II Device <strong>Handbook</strong>, Volume 2 May 2007

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!