Configuration Handbook - Kamami.pl

3. Altera EnhancedConfiguration DevicesS52014-2.3IntroductionConcurrentConfigurationThe latest enhanced configuration devices from Altera ® address the needfor high-density configuration solution by combining industry-standardflash memory with a feature-rich configuration controller. A single-chipconfiguration solution provides designers with several new andadvanced features that significantly reduce configuration times. Thischapter discusses the hardware and software implementation ofenhanced configuration device features such as concurrent and dynamicconfiguration, data compression, clock division, and an external flashmemory interface. Enhanced configuration devices include EPC4, EPC8,and EPC16 devices.Configuration data is transmitted from the enhanced configurationdevice to the SRAM-based device on the DATA lines. The DATA lines areoutputs on the enhanced configuration devices, and inputs to the SRAMbaseddevices.These DATA lines correspond to the Bitn lines in the ConvertProgramming Files window in the Altera Quartus ® II software. Forexample, if you specify a SRAM Object File (.sof) to use Bit0 in theQuartus II software, that .sof will be transmitted on the DATA[0] linefrom the enhanced configuration device to the SRAM-based device.Enhanced configuration devices can concurrently configure a number ofdevices with a variety of supported configuration schemes.Supported Schemes & GuidelinesBy using enhanced configuration devices, there are several different waysto configure Altera SRAM-based programmable logic devices (PLDs):■■■■■1-bit passive serial (PS)2-bit PS4-bit PS8-bit PSFast passive parallel (FPP)Additionally, you can use these configuration schemes in conjunctionwith the dynamic configuration option (previously called page modeoperation) for sophisticated configuration setups.Altera Corporation 3–1April 2007