Configuration Handbook - Kamami.pl

Configuring Stratix & Stratix GX DevicesTable 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device (Part 5 of 8)Pin NameUser ModeConfigurationSchemenCEO N/A All Multi-DeviceSchemesDCLK N/A Synchronousconfigurationschemes(PS, FPP)Pin TypeOutputInput(PS, FPP)DescriptionOutput that drives low when deviceconfiguration is complete. In single deviceconfiguration, this pin is left floating. In multideviceconfiguration, this pin feeds the nextdevice’s nCE pin. The nCEO of the last devicein the chain is left floating.The voltage levels driven out by this pin aredependent on the V CCIO of the I/O bank itresides in.In PS and FPP configuration, DCLK is the clockinput used to clock data from an externalsource into the target device. Data is latchedinto the FPGA on the rising edge of DCLK.In PPA mode, DCLK should be tied high to V CCto prevent this pin from floating.After configuration, this pin is tri-stated. Inschemes that use a configuration device,DCLK is driven low after configuration is done.In schemes that use a control host, DCLKshould be driven either high or low, whicheveris more convenient. Toggling this pin afterconfiguration does not affect the configureddevice. This pin uses Schmitt trigger inputbuffers.DATA0 I/O PS, FPP, PPA Input Data input. In serial configuration modes, bitwideconfiguration data is presented to thetarget device on the DATA0 pin. The V IH andV IL levels for this pin are dependent on theV CCIO of the I/O bank that it resides in.After configuration, DATA0 is available as auser I/O and the state of this pin depends onthe Dual-Purpose Pin settings.After configuration, EPC1 and EPC1441devices tri-state this pin, while enhancedconfiguration and EPC2 devices drive this pinhigh.Altera Corporation 11–55July 2005 Stratix Device Handbook, Volume 2