Configuration Handbook - Kamami.pl

Passive Parallel Synchronous ConfigurationfFor more information on how to use the USB Blaster, MasterBlaster,ByteBlaster II, or ByteBlasterMV cables, refer to the following datasheets:■■■■USB Blaster USB Port Download Cable Data SheetMasterBlaster Serial/USB Communications Cable Data SheetByteBlaster II Parallel Port Download Cable Data SheetByteBlasterMV Parallel Port Download Cable Data SheetPassive ParallelSynchronousConfigurationPassive Parallel Synchronous (PPS) configuration uses an intelligent host,such as a microprocessor, to transfer configuration data from a storagedevice, such as flash memory, to the target APEX 20KE or APEX 20KCdevice. Configuration data can be stored in TTF, RBF, or HEX format. Thehost system outputs byte-wide data and the serializing clock to the FPGA.The target device latches the byte-wide data on the DATA[7..0] pins onthe rising edge of DCLK and then uses the next eight falling edges on DCLKto serialize the data internally. On the ninth rising DCLK edge, the nextbyte of configuration data is latched into the target device. Figure 7–16shows the configuration interface connections between the FPGA and amicroprocessor for single device configuration.Figure 7–16. Single Device PPS Configuration Using a MicroprocessorMemoryADDR DATA[7..0]Microprocessor(1) V CC V CC (1)10 kΩ10 kΩGNDV CCGNDAPEX 20KE orAPEX 20KC DeviceMSEL0MSEL1CONF_DONEnSTATUSnCEDATA[7..0]DCLKnCONFIGNote to Figure 7–16:(1) The pull-up resistor should be connected to a supply that provides an acceptableinput signal for the device.7–34 Altera CorporationConfiguration Handbook, Volume 1 August 2005