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Configuration Handbook - Kamami.pl

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IntroductionfFor information on enhanced configuration devices, refer to the Enhanced<strong>Configuration</strong> Devices (EPC4, EPC8 and EPC16) Data Sheet and the UsingAltera Enhanced <strong>Configuration</strong> Devices chapters in volume 2 of the<strong>Configuration</strong> <strong>Handbook</strong>.1 The largest enhanced configuration device supports 16 MBits ofconfiguration bitstream. You may need to use the MAX IIdevice, or use a microprocessor using a flash memoryconfiguration method, or use the compression feature, to reducethe configuration file size of large Stratix III devices.The Altera serial configuration devices (EPCS128, EPCS64, and EPCS16)support a single-device configuration solution for Stratix III devices andare used in the fast AS configuration scheme. Serial configuration devicesoffer a low-cost, low-pin count configuration solution.fFor information on serial configuration devices, refer to the Serial<strong>Configuration</strong> Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128)Data Sheet in volume 2 of the <strong>Configuration</strong> <strong>Handbook</strong>.1 The largest serial configuration device currently supports64 MBits of configuration bitstream.<strong>Configuration</strong> SchemesSelect the configuration scheme by driving the Stratix III device MSELpins either high or low, as shown in Table 11–1. The MSEL pins arepowered by the V CCPGM power sup<strong>pl</strong>y of the bank they reside in. TheMSEL[2..0] pins have 5-kΩ internal pull-down resistors that are alwaysactive. During power-on reset (POR) and during reconfiguration, theMSEL pins have to be at LVTTL V IL and V IH levels to be considered a logiclow and logic high.1 To avoid any problems with detecting an incorrect configurationscheme, hard-wire the MSEL[] pins to V CCPGM and GND,without any pull-up or pull-down resistors. Do not drive theMSEL[] pins by a microprocessor or another device.Table 11–1. Stratix III <strong>Configuration</strong> Schemes (Part 1 of 2)<strong>Configuration</strong> Scheme MSEL2 MSEL1 MSEL0Fast passive parallel (FPP) 0 0 0Passive serial (PS) 0 1 011–2 Altera CorporationStratix III Device <strong>Handbook</strong>, Volume 1 May 2007

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