Configuration Handbook - Kamami.pl

Fast Passive Parallel ConfigurationUpon power-up, the Stratix II and Stratix II GX devices go through aPower-On Reset (POR). The POR delay is dependent on the PORSEL pinsetting; when PORSEL is driven low, the POR time is approximately100 ms, if PORSEL is driven high, the POR time is approximately 12 ms.During POR, the device resets, holds nSTATUS low, and tri-states all userI/O pins. Once the device successfully exits POR, all user I/O pinscontinue to be tri-stated. If nIO_pullup is driven low during power-upand configuration, the user I/O pins and dual-purpose I/O pins haveweak pull-up resistors, which are on (after POR) before and duringconfiguration. If nIO_pullup is driven high, the weak pull-up resistorsare disabled.1 You can hold nConfig low in order to stop deviceconfiguration.fThe value of the weak pull-up resistors on the I/O pins that are on beforeand during configuration can be found in the DC & SwitchingCharacteristics chapter in the Stratix II Device Handbook or the Stratix II GXDevice Handbook.The configuration cycle consists of three stages: reset, configuration andinitialization. While nCONFIG or nSTATUS are low, the device is in thereset stage. To initiate configuration, the MAX II device must drive thenCONFIG pin from low-to-high.1 V CCINT , V CCIO , and V CCPD of the banks where the configurationand JTAG pins reside need to be fully powered to theappropriate voltage levels in order to begin the configurationprocess.When nCONFIG goes high, the device comes out of reset and releases theopen-drain nSTATUS pin, which is then pulled high by an external 10-kΩpull-up resistor. Once nSTATUS is released, the device is ready to receiveconfiguration data and the configuration stage begins. When nSTATUS ispulled high, the MAX II device places the configuration data one byte ata time on the DATA[7..0] pins.1 Stratix II and Stratix II GX devices receive configuration data onthe DATA[7..0] pins and the clock is received on the DCLK pin.Data is latched into the device on the rising edge of DCLK. If youare using the Stratix II or Stratix II GX decompression and/ordesign security feature, configuration data is latched on therising edge of every fourth DCLK cycle. After the configurationdata is latched in, it is processed during the following threeDCLK cycles.7–16 Altera CorporationStratix II Device Handbook, Volume 2 May 2007