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Configuration Handbook - Kamami.pl

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<strong>Configuration</strong> SchemesTable 11–7 shows the status of the device DATA pins during and afterconfiguration.Table 11–7. DATA Pin Status Before & After <strong>Configuration</strong>Stratix or Stratix GX DevicePinsDuringAfterDATA0 (1) Used for configuration User definedDATA[7..1] (2) Used in some configuration modes User definedI/O Pins Tri-state User definedNotes to Table 11–7:(1) The status shown is for configuration with a configuration device.(2) The function of these pins depends upon the settings specified in the Quartus IIsoftware using the Device & Pin Option dialog box (see the Software Settingssection in the <strong>Configuration</strong> <strong>Handbook</strong>, Volume 2, and the Quartus II Help softwarefor more information).PS <strong>Configuration</strong> with a Download CableIn PS configuration with a download cable, an intelligent host transfersdata from a storage device to the Stratix or Stratix GX device through theMasterBlaster, USB-Blaster, ByteBlaster II or ByteBlasterMV cable. Toinitiate configuration in this scheme, the download cable generates alow-to-high transition on the nCONFIG pin. The programming hardwarethen <strong>pl</strong>aces the configuration data one bit at a time on the device’s DATA0pin. The data is clocked into the target device until CONF_DONE goes high.The CONF_DONE pin must have an external 10-kΩ pull-up resistor inorder for the device to initialize.When using programming hardware for the Stratix or Stratix GX device,turning on the Auto-Restart <strong>Configuration</strong> on Frame Error option doesnot affect the configuration cycle because the Quartus II software mustrestart configuration when an error occurs. Additionally, the EnableUser-Sup<strong>pl</strong>ied Start-Up Clock (CLKUSR) option has no affect on thedevice initialization since this option is disabled in the SOF whenprogramming the FPGA using the Quartus II software programmer anda download cable. Therefore, if you turn on the CLKUSR option, you donot need to provide a clock on CLKUSR when you are configuring theFPGA with the Quartus II programmer and a download cable.Figure 11–5 shows PS configuration for the Stratix or Stratix GX deviceusing a MasterBlaster, USB-Blaster, ByteBLaster II or ByteBlasterMVcable.11–14 Altera CorporationStratix Device <strong>Handbook</strong>, Volume 2 July 2005

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